-------------------------8<------------------------
$ iverilog -tfpga -o test.edif test.v
test.v:8: warning: Process not synthesized.
------------------------->8------------------------
The test code that produces this is as follows:
-------------------------8<------------------------
module test (D, clk, en, Q);
input D, clk, en;
output Q;
reg Q;
always @(clk) // this is line 8
begin
if(en==1)
begin
Q = D;
end
end
endmodule
------------------------->8------------------------
It's perfectly valid Verilog code, but its not being synthesized??
What's up with that?
Thanks, -d
