From: Al Davis <[EMAIL PROTECTED]> Subject: Re: gEDA-user: PCB suggestion Date: Fri, 7 Jan 2005 12:27:49 -0500 Message-ID: <[EMAIL PROTECTED]>
> On Friday 07 January 2005 11:38 am, Daniel J Wisehart wrote: > > Why not use a neutral standard like XML? > > Because XML really doesn't say much. All it really does is to > specify a syntax based on tags like <foo> to begin a scope > named foo, and </foo> to end it. Everything meaningful is > specified in DTD files. Indeed, and you need to make those design-choices with great care, or else you have just wasted alot of time and effort, again, and it will not be easy to agree on anything. Also, there already exists (at least) 2 EDA standards based on XML. Both from IPC. Having looked on them, they addresses many good points, but doesn't solve everything. > You could make an equal statement by asking it to be C-like. > All this says is to use curly-braces, and a C-like syntax. It > is equally valid, but also equally useless because it doesn't > say what is needed to communicate. You can also end up with a big mess if you don't specify how little the C-likeness is actually carried. I agree with the point that regardless of which grammar base (may it be XML, C, VHDL or LISP - all being in such use today) you are using, it is the detailed syntax, grammar and semantics which goes in there which needs to be well thought. Here the devil is very much in the details. > What is important is all of the information that relates to > circuits. This is where a full language like VHDL comes in. A > VHDL-like language using XML syntax would be equally valid > except that it isn't a standard. I don't particularly like the > ADA-like syntax choices that VHDL made, but that is a minor > point that I can live with. Regardless of how much we like ADA, VHDL has a strictness and formalism which when properly used (fairly simple to learn) is a big support. VHDL is a good structure to build upon IMHO. There already exists a number of profiled VHDL standards, where the VHDL grammar, syntax and semantics have been reduced to a subset for specific purposes and that works well it seems. I think about VITAL models, WAVES and BSDL. I am sure there exists more such formats. I especially like the entity/architecture division and the way one may use it at instantiation together with the generics. The configuration stuff may be a bit confusing thought. The VHDL infrastructure is a good building-block. Profile it properly. Some of the things I like to see isn't naturally handled in VHDL, but it can be added. Cheers, Magnus
