Hi John, > > Another suggestion: > > Would it be possible to define (preferences) a default directory for > models and subcircuits? That way it would not be necessary to define the > entire path in each of the components. To remain compatible, I'd suggest > that 'file' attributes starting with / be absolute, else use the default > directory. >
Wouldn't it be useful to work with variables like “$lib/model_xy” The variable must be defined in a setup file or in the shell. But this requires programming work. So far, until this is done, I can show you my way. I use the “spice-include” symbol and add to the file attribute <name>.spc. This file includes all the models and simulation command. All you need in your schematic is a single symbol. You can run ngspice in batch mode. An example is attached. Peter
*---------------------------------------------- * <filename>.spc; Spice comand file * include this to your spice netlist * later this might be derived from sim.cmd *---------------------------------------------- * Change Log * 06. Feb. 2005 -- V 1.0 start hacking * * semiconductor model library *.include /home/peter/gEDA/library_spice/open_tech_lib/peter.lib *.include /home/peter/gEDA/library_spice/open_tech_lib/level_1_short.lib *.include /home/peter/gEDA/library_spice/open_tech_lib/level_3_typ.lib .include /home/peter/gEDA/library_spice/XFAB_XC06_primitive/models_tt.lib *.include /home/peter/gEDA/library_spice/700/?? * semiconductor macros *.include /home/peter/gEDA/library_spice/XFAB_XC06_cells_analog/aporc02_subcir.spc *.include /home/peter/gEDA/library_spice/XFAB_XC06_cells_digital/AND2LX1.spc * options *.OPTIONS temp=25 *.OPTIONS gmin=1e-12 .control *set xxx=2 *echo $xxx set filetype = ascii foreach n 0 1 2 3 4 5 echo n alter vgs = $n dc vds 0 5 0.1 plot -i(vds) write $n i(vds) end ************* *dc vds 0 5 0.1 *plot -i(vds) *alter vgs = 2V *dc vds 0 5 0.1 *plot -i(vds) ************* * foreach tempval -20 0 20 40 60 80 100 120 140 * set temp=$tempval * op * print vbgp * end .endc *------------ * analysis *------------ * operating point *.op * dc tranfer * .dc <quelle> <start> <stop> <step> <<quelle2> <start> <stop> <step>> *.dc vds 0 5 1 vgs 0 5 0.1 *.dc vds 0 5 0.1 *.print dc i(vds) * transient * .tran <tstep> <tstop> * .tran 100n 50u * small signal ac ************ * debug ************ * show * showmod * trace * step * nodeset * ic
