gene wrote:
I don't use Icarus Verilog, so I won't/can't comment on your problems
there. But I did notice something with your code . . .
always @ (posedge Clk) begin
DtaRcd = DtaRcd >> 1;
DtaRcd[39] = DtaIn;
corr = DtaRcd ~^ `CorrFrame;
end
This code may not conform to "standard" coding practices, but it is
definitely correct, and should be handled 100% by commercial synthesis
tools as well as simulators.
Firstly, you may want to change the "=" to "<=". The "=" is the
blocking form and may not be what you desired. I see that you are
creating a shift reg with DtaIn as the new data. I don't believe this
will build correctly. The correct code would be something like:
always @ (posedge Clk) begin
DtaRcd <= DtaRcd >> 1;
DtaRcd[39] <= DtaIn;
corr <= DtaRcd ~^ `CorrFrame;
end
No, this code is incorrect.
Replacing a '=' with '<=' without understanding the consequences is not
a good idea.
In the original example, DataRcd and corr will all be registers
(flip-flops), which will all be correct on the same cycle.
In your "correction" you have a mistake because bit 39 is driven both as
part of "DataRc <= DataRcd >> 1" as well as in "DataRcd[39] <= DtaIn".
For blocking assignments this is legal, and the correct interpretation
(without going into lengthly explanations it is correct for this
example) is to take the last value.
now, "corr" in his example will correctly be driven by the value of
DataRcd and CorrFrame from the same clock cycle, while in your example,
corr will lag by 1 clock cycle.
or, more simply:
always @ (posedge Clk) begin
DtaRcd <= {DtaIn,DtaRcd[39:1]};
corr = DtaRcd ~^ `CorrFrame;
end
This code is correct.
have fun!
gene
udi
On Sun, 07 Aug 2005 15:50:51 -0400, Harold D. Skank
<[EMAIL PROTECTED]> wrote:
People,
I'm using Icarus Verilog as a front end to some Lattice tools.
Basically I have two questions, an immediate procedural question, then a
longer term question regarding how to write some ancillary programs.
The procedural question: I've attached the programs I'm currently
attempting to run. When I call the ./vlogTST program (also attached) I
get the following output on the control console. Please ignore the
syntax error info associated with v:37, I know about that and will
eventually get it corrected. What I don't understand is what the v:51:
message is trying to tell me.
[EMAIL PROTECTED] RcvAlg]$ ./vlogTST
/home/designer/Etrema/RcvAlg/testfixture.v:37: syntax error
/home/designer/Etrema/RcvAlg/testfixture.v:37: error: malformed
statement
testfixture.v:37: syntax error
testfixture.v:37: error: malformed statement
testfixture.v:51: Module testfixture was already declared
here: /home/designer/Etrema/RcvAlg/testfixture.v:14
For the second question, the old iverilog-fpga man page (apparently
older than the current iverilog man page) referring to the parch=lpm
option indicates that users may write interface libraries to connect
netlists to vendor architecture. I'm using Lattice devices, and have to
go through an involved procedure to get from the behavioral code to the
EDIF model acceptable to my Lattice compiler. First of all, is this
possibility (writing the interface library) still available, and if so,
could you give me some clues about how to start?
Thank you for your consideration.
Harold Skank
