Astonishing. Thanks! So, are amazing little tidbits like this one written up somewhere in one place? If not, should this go in the Wiki page?
Thanks, Marshall -----Original Message----- From: [EMAIL PROTECTED] on behalf of DJ Delorie Sent: Mon 1/9/2006 9:14 PM To: [email protected] Subject: Re: gEDA-user: Vias with zero clearance in PCB? > I'd like to place numerous vias in a cluster to assist with heat > transfer or RF shielding integrity. How can I do this in PCB? If what you mean is "I'd like a bunch of vias with solid connections to the plane, without thermals or clearance" then the only way to do so is to add a second polygon in that area that does not have the "clear pins/vias" flag set. Amusingly, the way to do this is to use the "change size" hotkeys (S or Shift-S) on the new polygon. There is currently no way to specify this on a per-via basis.
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