Samuel A. Falvo II wrote:
On 2/21/06, DJ Delorie <[EMAIL PROTECTED]> wrote:
inverter gate. You need to name the nets differently *anyway*.
___
AEN AEN
-------|>o-------
AEN DEN (data enable)
-------|>o-------
AEN ADIS (address disable)
-------|>o-------
___
TXD
-------|>=======
TXD
TXNEG
-------|>=======
TXPOS
TXB (transmit balance)
-------|>=======
TXCB (transmit counter-balance)
TXR (transmit ring)
-------|>=======
TXT (transmit tip)
The bar's significance stems from boolean algebra, and carries no
intrinsic meaning of intent. I think, as with self-documenting
software, self-documenting hardware designs are more important.
Signals should describe what they do as much as possible. Case in
point: NRFD and NDAC from the GPIB bus. Every signal on GPIB is
active low, so they just don't bother with the overbar there.
Instead, they use more descriptive names instead (Not Ready For Data
and No Data Accepted, respectively).
--
Samuel A. Falvo II
Cool examples, Sam - thanks. I agree completely with you. Name the
nets descriptively, that's the ticket. I was trying to say, probably
poorly, that it works out pretty well.
For me, this stuff started back in the ABEL days. For example(if I
remember my abel):
pin a;
pin b;
pin c;
c = a + b;
this is an "OR" gate, right?
OK, now change the pin descriptions with all active lows:
pin !a;
pin !b;
pin !c;
c = a + b;
Still an "or" gate? Sort of. It's really a NAND gate - but I can read
it as C is true when A is true or B is true. Who cares that it's active
high or low. The only time I really care is at the actual IO of the
chip. I could rename A,B and C more usefully as:
A = I_Have_Cash
B = I_Have_Credit
C = I_Can_Buy_You_All_A_Beer
so, I can buy beer if I have cash, or have credit or both (but the beer
can't be bud, ok? I like Sam Adams). The active level doesn't really
seem relevant here - but the logical sense is all that really matters.
This stuff works for verilog, vhdl, schematics - whatever.
