changeset 3bb902f4e99a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3bb902f4e99a
description:
inorder: update event priorities
dont use offset to calculate this but rather an enum
that can be updated
diffstat:
src/cpu/inorder/cpu.cc | 11 +++++------
src/cpu/inorder/cpu.hh | 9 +++++++--
src/cpu/inorder/resource_pool.cc | 2 +-
src/cpu/inorder/resource_pool.hh | 4 ++++
src/cpu/inorder/resources/fetch_seq_unit.cc | 3 ++-
5 files changed, 19 insertions(+), 10 deletions(-)
diffs (109 lines):
diff -r cd9dd7f8125f -r 3bb902f4e99a src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:36 2011 -0400
+++ b/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:36 2011 -0400
@@ -90,9 +90,8 @@
InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
Fault fault, ThreadID _tid, DynInstPtr inst,
- unsigned event_pri_offset)
- : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
- cpu(_cpu)
+ CPUEventPri event_pri)
+ : Event(event_pri), cpu(_cpu)
{
setEvent(e_type, fault, _tid, inst);
}
@@ -836,10 +835,10 @@
void
InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
ThreadID tid, DynInstPtr inst,
- unsigned delay, unsigned event_pri_offset)
+ unsigned delay, CPUEventPri event_pri)
{
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
- event_pri_offset);
+ event_pri);
Tick sked_tick = nextCycle(curTick() + ticks(delay));
if (delay >= 0) {
@@ -1064,7 +1063,7 @@
// threads after we've finished deactivating, squashing,etc.
// other threads
scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
- delay, 5);
+ delay, ActivateNextReadyThread_Pri);
// Be sure to signal that there's some activity so the CPU doesn't
// deschedule itself.
diff -r cd9dd7f8125f -r 3bb902f4e99a src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:36 2011 -0400
+++ b/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:36 2011 -0400
@@ -190,6 +190,11 @@
static std::string eventNames[NumCPUEvents];
+ enum CPUEventPri {
+ InOrderCPU_Pri = Event::CPU_Tick_Pri,
+ ActivateNextReadyThread_Pri = Event::CPU_Tick_Pri + 10
+ };
+
/** Define CPU Event */
class CPUEvent : public Event
{
@@ -206,7 +211,7 @@
public:
/** Constructs a CPU event. */
CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
- ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
+ ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
/** Set Type of Event To Be Scheduled */
void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
@@ -235,7 +240,7 @@
/** Schedule a CPU Event */
void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
DynInstPtr inst, unsigned delay = 0,
- unsigned event_pri_offset = 0);
+ CPUEventPri event_pri = InOrderCPU_Pri);
public:
/** Interface between the CPU and CPU resources. */
diff -r cd9dd7f8125f -r 3bb902f4e99a src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Sun Jun 19 21:43:36 2011 -0400
+++ b/src/cpu/inorder/resource_pool.cc Sun Jun 19 21:43:36 2011 -0400
@@ -508,7 +508,7 @@
int stage_num,
InstSeqNum seq_num,
ThreadID _tid)
- : Event(CPU_Tick_Pri), resPool(_resPool),
+ : Event(ResPool_Pri), resPool(_resPool),
eventType(e_type), inst(_inst), seqNum(seq_num),
stageNum(stage_num), tid(_tid)
{ }
diff -r cd9dd7f8125f -r 3bb902f4e99a src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Sun Jun 19 21:43:36 2011 -0400
+++ b/src/cpu/inorder/resource_pool.hh Sun Jun 19 21:43:36 2011 -0400
@@ -67,6 +67,10 @@
Default
};
+ enum ResPoolEventPri {
+ ResPool_Pri = InOrderCPU::InOrderCPU_Pri - 5
+ };
+
class ResPoolEvent : public Event
{
protected:
diff -r cd9dd7f8125f -r 3bb902f4e99a src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:36
2011 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:36
2011 -0400
@@ -165,7 +165,8 @@
// A Trap Caused This Fault and will update the pc state
// when done trapping
DPRINTF(InOrderFetchSeq, "[tid:%i] Blocking due to fault @ "
- "[sn:%i].\n", inst->seqNum);
+ "[sn:%i].%s %s \n", inst->seqNum,
+ inst->instName(), inst->pcState());
pcValid[tid] = false;
} else {
TheISA::PCState nextPC;
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
