changeset 440835b0179a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=440835b0179a
description:
inorder: branch predictor update
only update BTB on a taken branch and update branch predictor w/pcstate
from instruction
---
only pay attention to branch predictor updates if the the inst. is in
fact a branch
diffstat:
src/cpu/inorder/cpu.cc | 3 +++
src/cpu/inorder/pipeline_stage.cc | 2 +-
src/cpu/inorder/resources/bpred_unit.cc | 6 ++++--
src/cpu/inorder/resources/branch_predictor.cc | 8 ++++++--
src/cpu/inorder/resources/fetch_seq_unit.cc | 6 +++---
5 files changed, 17 insertions(+), 8 deletions(-)
diffs (88 lines):
diff -r 1f215de12d15 -r 440835b0179a src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:37 2011 -0400
@@ -506,6 +506,9 @@
W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
}
+ if (inst->isControl())
+ W.needs(BPred, BranchPredictor::UpdatePredictor);
+
// Insert Back Schedule into our cache of
// resource schedules
addToSkedCache(inst, res_sked);
diff -r 1f215de12d15 -r 440835b0179a src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/pipeline_stage.cc Sun Jun 19 21:43:37 2011 -0400
@@ -420,7 +420,7 @@
while (cur_it != end_it) {
if ((*cur_it)->seqNum <= squash_seq_num) {
DPRINTF(InOrderStage, "[tid:%i]: Cannot remove skidBuffer "
- "instructions (starting w/[sn:%i]) before delay slot "
+ "instructions (starting w/[sn:%i]) before "
"[sn:%i]. %i insts left.\n", tid,
(*cur_it)->seqNum, squash_seq_num,
skidBuffer[tid].size());
diff -r 1f215de12d15 -r 440835b0179a src/cpu/inorder/resources/bpred_unit.cc
--- a/src/cpu/inorder/resources/bpred_unit.cc Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/resources/bpred_unit.cc Sun Jun 19 21:43:37 2011 -0400
@@ -250,7 +250,7 @@
tid, asid, inst->pcState(), target);
} else {
DPRINTF(InOrderBPred, "[tid:%i]: BTB doesn't have a "
- "valid entry.\n",tid);
+ "valid entry, predicting false.\n",tid);
pred_taken = false;
}
}
@@ -369,7 +369,9 @@
BPUpdate((*hist_it).pc.instAddr(), actually_taken,
pred_hist.front().bpHistory);
- BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
+ // only update BTB on branch taken right???
+ if (actually_taken)
+ BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
DPRINTF(InOrderBPred, "[tid:%i]: Removing history for [sn:%i] "
"PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc);
diff -r 1f215de12d15 -r 440835b0179a
src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc Sun Jun 19 21:43:37
2011 -0400
+++ b/src/cpu/inorder/resources/branch_predictor.cc Sun Jun 19 21:43:37
2011 -0400
@@ -152,10 +152,14 @@
DPRINTF(InOrderBPred, "[tid:%i][sn:%i] Squashing...\n", tid,
bpred_squash_num);
+ // update due to branch resolution
if (squash_stage >= ThePipeline::BackEndStartStage) {
- bool taken = inst->predTaken();
- branchPred.squash(bpred_squash_num, inst->readPredTarg(), taken, tid);
+ branchPred.squash(bpred_squash_num,
+ inst->pcState(),
+ inst->pcState().branching(),
+ tid);
} else {
+ // update due to predicted taken branch
branchPred.squash(bpred_squash_num, tid);
}
}
diff -r 1f215de12d15 -r 440835b0179a src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:37
2011 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:37
2011 -0400
@@ -79,13 +79,13 @@
ThreadID tid = inst->readTid();
int stage_num = fs_req->getStageNum();
- DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
- pc[tid]);
-
switch (fs_req->cmd)
{
case AssignNextPC:
{
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
+ pc[tid]);
+
if (pcValid[tid]) {
inst->pcState(pc[tid]);
inst->setMemAddr(pc[tid].instAddr());
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
