changeset f4a37a07b97c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f4a37a07b97c
description:
inorder: SE mode TLB faults
handle them like we do in FS mode, by blocking the TLB until the fault
is handled by the fault->invoke()
diffstat:
src/cpu/inorder/resource.cc | 17 +++++++--------
src/cpu/inorder/resources/cache_unit.cc | 37 +++++++++++++++++---------------
src/cpu/inorder/resources/cache_unit.hh | 3 ++
src/cpu/inorder/resources/use_def.cc | 18 ++++++++--------
4 files changed, 40 insertions(+), 35 deletions(-)
diffs (164 lines):
diff -r 5db2bac0a900 -r f4a37a07b97c src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Sun Jun 19 21:43:42 2011 -0400
+++ b/src/cpu/inorder/resource.cc Sun Jun 19 21:43:42 2011 -0400
@@ -46,7 +46,8 @@
Resource::Resource(string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu)
: resName(res_name), id(res_id),
- width(res_width), latency(res_latency), cpu(_cpu)
+ width(res_width), latency(res_latency), cpu(_cpu),
+ resourceEvent(NULL)
{
reqs.resize(width);
@@ -75,15 +76,13 @@
// If the resource has a zero-cycle (no latency)
// function, then no reason to have events
// that will process them for the right tick
- if (latency > 0) {
- resourceEvent = new ResourceEvent[width];
- } else {
- resourceEvent = NULL;
- }
+ if (latency > 0)
+ resourceEvent = new ResourceEvent[width];
- for (int i = 0; i < width; i++) {
- reqs[i] = new ResourceRequest(this);
- }
+
+ for (int i = 0; i < width; i++)
+ reqs[i] = new ResourceRequest(this);
+
initSlots();
}
diff -r 5db2bac0a900 -r f4a37a07b97c src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sun Jun 19 21:43:42 2011 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Sun Jun 19 21:43:42 2011 -0400
@@ -178,10 +178,6 @@
reqs[i] = new CacheRequest(this);
}
- // Currently Used to Model TLB Latency. Eventually
- // Switch to Timing TLB translations.
- resourceEvent = new CacheUnitEvent[width];
-
cacheBlkSize = this->cachePort->peerBlockSize();
cacheBlkMask = cacheBlkSize - 1;
@@ -433,30 +429,22 @@
ThreadContext *tc = cpu->thread[tid]->getTC();
PCState old_pc = tc->pcState();
tc->pcState() = inst->pcState();
+
inst->fault =
_tlb->translateAtomic(cache_req->memReq, tc, tlb_mode);
tc->pcState() = old_pc;
if (inst->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
- "addr:%08p for [sn:%i].\n", tid, inst->fault->name(),
+ "addr:%08p for [sn:%i].\n", tid, tlb_fault->name(),
cache_req->memReq->getVaddr(), inst->seqNum);
tlbBlocked[tid] = true;
tlbBlockSeqNum[tid] = inst->seqNum;
-#if !FULL_SYSTEM
- unsigned stage_num = cache_req->getStageNum();
-
- cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
- cache_req->tlbStall = true;
-
- // schedule a time to process the tlb miss.
- // latency hardcoded to 1 (for now), but will be updated
- // when timing translation gets added in
- unsigned slot_idx = cache_req->getSlot();
- scheduleEvent(slot_idx, 1);
-#endif
+ // Make sure nothing gets executed until after this faulting
+ // instruction gets handled.
+ inst->setSerializeAfter();
// Mark it as complete so it can pass through next stage.
// Fault Handling will happen at commit/graduation
@@ -467,8 +455,15 @@
cache_req->memReq->getVaddr(),
cache_req->memReq->getPaddr());
}
+}
+#if !FULL_SYSTEM
+void
+CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+{
+ tlbBlocked[tid] = false;
}
+#endif
Fault
CacheUnit::read(DynInstPtr inst, Addr addr,
@@ -703,6 +698,14 @@
return;
}
+ if (inst->isSquashed()) {
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: Detected squashed instruction "
+ "next stage.\n", inst->readTid(), inst->seqNum);
+ finishCacheUnitReq(inst, cache_req);
+ return;
+ }
+
#if TRACING_ON
ThreadID tid = inst->readTid();
std::string acc_type = "write";
diff -r 5db2bac0a900 -r f4a37a07b97c src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Sun Jun 19 21:43:42 2011 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh Sun Jun 19 21:43:42 2011 -0400
@@ -157,6 +157,9 @@
bool processSquash(CacheReqPacket *cache_pkt);
+#if !FULL_SYSTEM
+ void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+#endif
void recvRetry();
/** Returns a specific port. */
diff -r 5db2bac0a900 -r f4a37a07b97c src/cpu/inorder/resources/use_def.cc
--- a/src/cpu/inorder/resources/use_def.cc Sun Jun 19 21:43:42 2011 -0400
+++ b/src/cpu/inorder/resources/use_def.cc Sun Jun 19 21:43:42 2011 -0400
@@ -159,15 +159,6 @@
InstSeqNum seq_num = inst->seqNum;
int ud_idx = ud_req->useDefIdx;
- if (inst->fault != NoFault) {
- DPRINTF(InOrderUseDef,
- "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
- "next stage.\n", inst->readTid(), inst->seqNum,
inst->fault->name(),
- inst->pcState());
- ud_req->done();
- return;
- }
-
if (serializeOnNextInst[tid] &&
seq_num > serializeAfterSeqNum[tid]) {
inst->setSerializeBefore();
@@ -187,6 +178,15 @@
serializeAfterSeqNum[tid] = seq_num;
}
+ if (inst->fault != NoFault) {
+ DPRINTF(InOrderUseDef,
+ "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
+ "next stage.\n", inst->readTid(), inst->seqNum,
inst->fault->name(),
+ inst->pcState());
+ ud_req->done();
+ return;
+ }
+
// If there is a non-speculative instruction
// in the pipeline then stall instructions here
// ---
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