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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. Diffs ----- src/arch/alpha/isa/mem.isa f12d1cd32cc7 src/arch/arm/isa/templates/mem.isa f12d1cd32cc7 src/arch/mips/isa/formats/mem.isa f12d1cd32cc7 src/arch/power/isa/formats/mem.isa f12d1cd32cc7 src/arch/sparc/isa/formats/mem/swap.isa f12d1cd32cc7 src/arch/sparc/isa/formats/mem/util.isa f12d1cd32cc7 src/arch/x86/isa/microops/ldstop.isa f12d1cd32cc7 src/cpu/base_dyn_inst.hh f12d1cd32cc7 src/cpu/exec_context.hh f12d1cd32cc7 src/cpu/inorder/inorder_dyn_inst.hh f12d1cd32cc7 src/cpu/inorder/inorder_dyn_inst.cc f12d1cd32cc7 src/cpu/simple/atomic.hh f12d1cd32cc7 src/cpu/simple/atomic.cc f12d1cd32cc7 src/cpu/simple/timing.hh f12d1cd32cc7 src/cpu/simple/timing.cc f12d1cd32cc7 Diff: http://reviews.m5sim.org/r/752/diff Testing ------- Thanks, Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
