changeset f0978919d459 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f0978919d459 description: inorder: sparc: add hello world regression - add InOrderCPU compile option to SPARC - add hello regression for SPARC
diffstat: build_opts/SPARC_SE | 2 +- tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini | 237 ++++++++ tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr | 2 + tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout | 10 + tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt | 267 ++++++++++ 5 files changed, 517 insertions(+), 1 deletions(-) diffs (truncated from 541 to 300 lines): diff -r f980df284118 -r f0978919d459 build_opts/SPARC_SE --- a/build_opts/SPARC_SE Mon Jun 20 18:58:31 2011 -0400 +++ b/build_opts/SPARC_SE Mon Jun 20 22:44:22 2011 -0400 @@ -1,4 +1,4 @@ TARGET_ISA = 'sparc' -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' FULL_SYSTEM = 0 PROTOCOL = 'MI_example' diff -r f980df284118 -r f0978919d459 tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini Mon Jun 20 22:44:22 2011 -0400 @@ -0,0 +1,237 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 + +[system.cpu] +type=InOrderCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +activity=0 +cachePorts=2 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +cpu_id=0 +dataMemPort=dcache_port +defer_registration=false +div16Latency=1 +div16RepeatRate=1 +div24Latency=1 +div24RepeatRate=1 +div32Latency=1 +div32RepeatRate=1 +div8Latency=1 +div8RepeatRate=1 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchBuffSize=4 +fetchMemPort=icache_port +functionTrace=false +functionTraceStart=0 +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +memBlockSize=64 +multLatency=1 +multRepeatRate=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +stageTracing=false +stageWidth=4 +system=system +threadModel=SMT +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=tests/test-progs/hello/bin/sparc/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff -r f980df284118 -r f0978919d459 tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr Mon Jun 20 22:44:22 2011 -0400 @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff -r f980df284118 -r f0978919d459 tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout Mon Jun 20 22:44:22 2011 -0400 @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jun 20 2011 19:27:12 +gem5 started Jun 20 2011 19:28:17 +gem5 executing on zooks +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 18208500 because target called exit() diff -r f980df284118 -r f0978919d459 tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt Mon Jun 20 22:44:22 2011 -0400 @@ -0,0 +1,267 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18208500 # Number of ticks simulated +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 40053 # Simulator instruction rate (inst/s) +host_tick_rate 136538838 # Simulator tick rate (ticks/s) +host_mem_usage 158968 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 5340 # Number of instructions simulated +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 36418 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 9732 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30132 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6286 # Number of cycles cpu stages are processed. +system.cpu.activity 17.260695 # Percentage of cycles cpu is active +system.cpu.comLoads 716 # Number of Load instructions committed +system.cpu.comStores 673 # Number of Store instructions committed +system.cpu.comBranches 1116 # Number of Branches instructions committed +system.cpu.comNops 173 # Number of Nop instructions committed +system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
