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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/760/
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
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X86: Fix store microops so they don't drop faults in timing mode.

If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.


Diffs
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  src/arch/x86/isa/microops/ldstop.isa 4adb1148ef73 

Diff: http://reviews.m5sim.org/r/760/diff


Testing
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Thanks,

Gabe

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