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Ship it! It is great to have this patch done. This is a big step in the integration process. - Brad On 2011-06-30 17:49:24, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/611/ > ----------------------------------------------------------- > > (Updated 2011-06-30 17:49:24) > > > Review request for Default. > > > Summary > ------- > > Ruby: Add support for functional accesses > This patch rpovides functional access support in Ruby. Currently only > the M5Port of RubyPort supports functional accesses. The support for > functional through the PioPort will be added as a separate patch. > > > Diffs > ----- > > configs/example/ruby_direct_test.py 4adb1148ef73 > configs/example/ruby_fs.py 4adb1148ef73 > configs/example/ruby_mem_test.py 4adb1148ef73 > configs/example/ruby_network_test.py 4adb1148ef73 > configs/example/ruby_random_test.py 4adb1148ef73 > configs/example/se.py 4adb1148ef73 > configs/ruby/MESI_CMP_directory.py 4adb1148ef73 > configs/ruby/MI_example.py 4adb1148ef73 > configs/ruby/MOESI_CMP_directory.py 4adb1148ef73 > configs/ruby/MOESI_CMP_token.py 4adb1148ef73 > configs/ruby/MOESI_hammer.py 4adb1148ef73 > configs/ruby/Ruby.py 4adb1148ef73 > src/cpu/testers/memtest/MemTest.py 4adb1148ef73 > src/cpu/testers/memtest/memtest.hh 4adb1148ef73 > src/cpu/testers/memtest/memtest.cc 4adb1148ef73 > src/mem/packet.hh 4adb1148ef73 > src/mem/packet.cc 4adb1148ef73 > src/mem/protocol/MESI_CMP_directory-L1cache.sm 4adb1148ef73 > src/mem/protocol/MESI_CMP_directory-L2cache.sm 4adb1148ef73 > src/mem/protocol/MESI_CMP_directory-dir.sm 4adb1148ef73 > src/mem/protocol/MESI_CMP_directory-dma.sm 4adb1148ef73 > src/mem/protocol/MI_example-cache.sm 4adb1148ef73 > src/mem/protocol/MI_example-dir.sm 4adb1148ef73 > src/mem/protocol/MI_example-dma.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_directory-L2cache.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_directory-dir.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_directory-dma.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_token-L1cache.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_token-L2cache.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_token-dir.sm 4adb1148ef73 > src/mem/protocol/MOESI_CMP_token-dma.sm 4adb1148ef73 > src/mem/protocol/MOESI_hammer-cache.sm 4adb1148ef73 > src/mem/protocol/MOESI_hammer-dir.sm 4adb1148ef73 > src/mem/protocol/MOESI_hammer-dma.sm 4adb1148ef73 > src/mem/protocol/RubySlicc_Exports.sm 4adb1148ef73 > src/mem/ruby/network/Network.cc 4adb1148ef73 > src/mem/ruby/network/Network.py 4adb1148ef73 > src/mem/ruby/profiler/Profiler.cc 4adb1148ef73 > src/mem/ruby/profiler/Profiler.py 4adb1148ef73 > src/mem/ruby/recorder/Tracer.cc 4adb1148ef73 > src/mem/ruby/recorder/Tracer.py 4adb1148ef73 > src/mem/ruby/slicc_interface/AbstractController.hh 4adb1148ef73 > src/mem/ruby/slicc_interface/Controller.py 4adb1148ef73 > src/mem/ruby/slicc_interface/SConscript 4adb1148ef73 > src/mem/ruby/system/Cache.py 4adb1148ef73 > src/mem/ruby/system/DirectoryMemory.cc 4adb1148ef73 > src/mem/ruby/system/DirectoryMemory.py 4adb1148ef73 > src/mem/ruby/system/RubyPort.hh 4adb1148ef73 > src/mem/ruby/system/RubyPort.cc 4adb1148ef73 > src/mem/ruby/system/RubySystem.py 4adb1148ef73 > src/mem/ruby/system/SConscript 4adb1148ef73 > src/mem/ruby/system/Sequencer.py 4adb1148ef73 > src/mem/ruby/system/System.hh 4adb1148ef73 > src/mem/ruby/system/System.cc 4adb1148ef73 > src/mem/slicc/ast/MemberExprAST.py 4adb1148ef73 > tests/configs/memtest-ruby.py 4adb1148ef73 > tests/configs/rubytest-ruby.py 4adb1148ef73 > tests/configs/simple-timing-mp-ruby.py 4adb1148ef73 > tests/configs/simple-timing-ruby.py 4adb1148ef73 > > Diff: http://reviews.m5sim.org/r/611/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
