changeset 559ef3da5dac in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=559ef3da5dac
description:
Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the
repository.
diffstat:
src/mem/ruby/slicc_interface/AbstractController.cc | 34 +++++++++++++++++
src/mem/ruby/system/Cache.py | 41 ++++++++++++++++++++
src/mem/ruby/system/DirectoryMemory.py | 43 ++++++++++++++++++++++
src/mem/ruby/system/SConscript | 3 +-
4 files changed, 120 insertions(+), 1 deletions(-)
diffs (144 lines):
diff -r 4e386e993ae8 -r 559ef3da5dac
src/mem/ruby/slicc_interface/AbstractController.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc Fri Jul 01
16:29:33 2011 -0500
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2011 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/ruby/slicc_interface/AbstractController.hh"
+
+AbstractController::AbstractController(const Params *p) : SimObject(p)
+{
+ p->ruby_system->registerAbstractController(this);
+}
diff -r 4e386e993ae8 -r 559ef3da5dac src/mem/ruby/system/Cache.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/system/Cache.py Fri Jul 01 16:29:33 2011 -0500
@@ -0,0 +1,41 @@
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Brad Beckmann
+
+from m5.params import *
+from m5.SimObject import SimObject
+from Controller import RubyController
+
+class RubyCache(SimObject):
+ type = 'RubyCache'
+ cxx_class = 'CacheMemory'
+ size = Param.MemorySize("capacity in bytes");
+ latency = Param.Int("");
+ assoc = Param.Int("");
+ replacement_policy = Param.String("PSEUDO_LRU", "");
+ start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
diff -r 4e386e993ae8 -r 559ef3da5dac src/mem/ruby/system/DirectoryMemory.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/system/DirectoryMemory.py Fri Jul 01 16:29:33 2011 -0500
@@ -0,0 +1,43 @@
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Brad Beckmann
+
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import SimObject
+
+class RubyDirectoryMemory(SimObject):
+ type = 'RubyDirectoryMemory'
+ cxx_class = 'DirectoryMemory'
+ version = Param.Int(0, "")
+ size = Param.MemorySize("1GB", "capacity in bytes")
+ use_map = Param.Bool(False, "enable sparse memory")
+ map_levels = Param.Int(4, "sparse memory map levels")
+ # the default value of the numa high bit is specified in the command line
+ # option and must be passed into the directory memory sim object
+ numa_high_bit = Param.Int("numa high bit")
diff -r 4e386e993ae8 -r 559ef3da5dac src/mem/ruby/system/SConscript
--- a/src/mem/ruby/system/SConscript Thu Jun 30 19:57:26 2011 -0500
+++ b/src/mem/ruby/system/SConscript Fri Jul 01 16:29:33 2011 -0500
@@ -33,8 +33,9 @@
if not env['RUBY']:
Return()
-SimObject('AbstractMemory.py')
+SimObject('Cache.py')
SimObject('Sequencer.py')
+SimObject('DirectoryMemory.py')
SimObject('MemoryControl.py')
SimObject('WireBuffer.py')
SimObject('RubySystem.py')
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