Yesterday, Brad, Steve and I were looking at code for TimingSimpleCPU.
There is a portion of the read/writeMem function that is not completely
explainable. I have copied the code below.
Addr split_addr = roundDown(addr + size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
assert(!req->isLLSC() && !req->isSwap());
req->splitOnVaddr(split_addr, req1, req2);
WholeTranslationState *state =
new WholeTranslationState(req, req1, req2, new uint8_t[size],
NULL, mode);
DataTranslation<TimingSimpleCPU> *trans1 =
new DataTranslation<TimingSimpleCPU>(this, state, 0);
DataTranslation<TimingSimpleCPU> *trans2 =
new DataTranslation<TimingSimpleCPU>(this, state, 1);
thread->dtb->translateTiming(req1, tc, trans1, mode);
thread->dtb->translateTiming(req2, tc, trans2, mode);
} else {
WholeTranslationState *state =
new WholeTranslationState(req, new uint8_t[size], NULL, mode);
DataTranslation<TimingSimpleCPU> *translation
= new DataTranslation<TimingSimpleCPU>(this, state);
thread->dtb->translateTiming(req, tc, translation, mode);
}
The code calls translateTiming() either once or twice depending on whether
or not the memory to be read lies in a single cache block. Should not the
check be that whether or no the memory to be read lies in a single page?
Thanks
Nilay
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