changeset 2a04edb07407 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a04edb07407
description:
O3: Update stats for fetch and bp changes.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini |
5 +-
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout |
10 +-
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt |
376 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |
5 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt |
776 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini |
5 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/00.gzip/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt |
778 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini |
3 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
736 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini |
5 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt |
728 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |
33 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr |
8 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |
22 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
3104 +++++----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |
33 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr |
8 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |
20 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
1700 ++--
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini |
4 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr |
18 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout |
22 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt |
1012 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status |
2 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal |
0
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini |
7 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/10.mcf/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt |
782 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini |
7 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout |
11 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt |
746 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini |
7 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/20.parser/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt |
818 +-
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini |
7 +-
tests/long/20.parser/ref/x86/linux/o3-timing/simout |
12 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt |
760 +-
tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini |
5 +-
tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout |
10 +-
tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt |
310 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini |
5 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr |
11 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |
20 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt |
962 +-
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini |
5 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/30.eon/ref/arm/linux/o3-timing/simout |
22 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt |
745 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini |
5 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |
791 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini |
5 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr |
2 -
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |
794 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini |
5 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout |
10 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt |
368 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini |
5 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt |
786 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini |
3 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/50.vortex/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt |
804 +-
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini |
5 +-
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout |
10 +-
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt |
298 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini |
5 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt |
784 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini |
5 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt |
797 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini |
5 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout |
14 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt |
336 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini |
5 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout |
14 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |
775 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini |
5 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simerr |
1 -
tests/long/70.twolf/ref/arm/linux/o3-timing/simout |
20 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt |
782 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini |
5 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout |
14 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt |
713 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini |
3 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout |
8 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt |
210 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt |
676 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr |
5 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout |
18 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt |
920 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/simerr |
1 -
tests/quick/00.hello/ref/arm/linux/o3-timing/simout |
20 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt |
696 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout |
10 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt |
200 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt |
671 +-
tests/quick/00.hello/ref/power/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/power/linux/o3-timing/simerr |
3 -
tests/quick/00.hello/ref/power/linux/o3-timing/simout |
18 +-
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt |
897 +-
tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini |
3 +-
tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout |
8 +-
tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt |
142 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt |
656 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini |
5 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr |
1 -
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout |
18 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt |
1477 ++--
tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini |
3 +-
tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout |
8 +-
tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt |
196 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini |
3 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout |
8 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
610 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini |
3 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
54 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
2851 ++++----
137 files changed, 16758 insertions(+), 16714 deletions(-)
diffs (truncated from 39443 to 300 lines):
diff -r 7a48916a32a8 -r 2a04edb07407
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini Sun Jul
10 12:56:08 2011 -0500
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini Sun Jul
10 12:56:09 2011 -0500
@@ -9,6 +9,7 @@
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -199,12 +200,12 @@
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 7a48916a32a8 -r 2a04edb07407
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout Sun Jul 10
12:56:08 2011 -0500
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout Sun Jul 10
12:56:09 2011 -0500
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 19 2011 07:12:22
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing
+gem5 compiled Jul 8 2011 15:00:53
+gem5 started Jul 8 2011 16:09:24
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ALPHA_SE/gem5.opt -d
build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -39,4 +39,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 279017416500 because target called exit()
+Exiting @ tick 274500333500 because target called exit()
diff -r 7a48916a32a8 -r 2a04edb07407
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt Sun Jul
10 12:56:08 2011 -0500
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt Sun Jul
10 12:56:09 2011 -0500
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.279017 #
Number of seconds simulated
-sim_ticks 279017416500 #
Number of ticks simulated
+sim_seconds 0.274500 #
Number of seconds simulated
+sim_ticks 274500333500 #
Number of ticks simulated
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 128000 #
Simulator instruction rate (inst/s)
-host_tick_rate 59339940 #
Simulator tick rate (ticks/s)
-host_mem_usage 192984 #
Number of bytes of host memory used
-host_seconds 4702.02 #
Real time elapsed on the host
+host_inst_rate 56944 #
Simulator instruction rate (inst/s)
+host_tick_rate 25971361 #
Simulator tick rate (ticks/s)
+host_mem_usage 245756 #
Number of bytes of host memory used
+host_seconds 10569.35 #
Real time elapsed on the host
sim_insts 601856964 #
Number of instructions simulated
system.cpu.dtb.fetch_hits 0 #
ITB hits
system.cpu.dtb.fetch_misses 0 #
ITB misses
system.cpu.dtb.fetch_acv 0 #
ITB acv
system.cpu.dtb.fetch_accesses 0 #
ITB accesses
-system.cpu.dtb.read_hits 114517555 #
DTB read hits
+system.cpu.dtb.read_hits 114517568 #
DTB read hits
system.cpu.dtb.read_misses 2631 #
DTB read misses
system.cpu.dtb.read_acv 0 #
DTB read access violations
-system.cpu.dtb.read_accesses 114520186 #
DTB read accesses
-system.cpu.dtb.write_hits 39666604 #
DTB write hits
+system.cpu.dtb.read_accesses 114520199 #
DTB read accesses
+system.cpu.dtb.write_hits 39666597 #
DTB write hits
system.cpu.dtb.write_misses 2302 #
DTB write misses
system.cpu.dtb.write_acv 0 #
DTB write access violations
-system.cpu.dtb.write_accesses 39668906 #
DTB write accesses
-system.cpu.dtb.data_hits 154184159 #
DTB hits
+system.cpu.dtb.write_accesses 39668899 #
DTB write accesses
+system.cpu.dtb.data_hits 154184165 #
DTB hits
system.cpu.dtb.data_misses 4933 #
DTB misses
system.cpu.dtb.data_acv 0 #
DTB access violations
-system.cpu.dtb.data_accesses 154189092 #
DTB accesses
-system.cpu.itb.fetch_hits 29078095 #
ITB hits
+system.cpu.dtb.data_accesses 154189098 #
DTB accesses
+system.cpu.itb.fetch_hits 27986226 #
ITB hits
system.cpu.itb.fetch_misses 22 #
ITB misses
system.cpu.itb.fetch_acv 0 #
ITB acv
-system.cpu.itb.fetch_accesses 29078117 #
ITB accesses
+system.cpu.itb.fetch_accesses 27986248 #
ITB accesses
system.cpu.itb.read_hits 0 #
DTB read hits
system.cpu.itb.read_misses 0 #
DTB read misses
system.cpu.itb.read_acv 0 #
DTB read access violations
@@ -41,16 +41,16 @@
system.cpu.itb.data_acv 0 #
DTB access violations
system.cpu.itb.data_accesses 0 #
DTB accesses
system.cpu.workload.num_syscalls 17 #
Number of system calls
-system.cpu.numCycles 558034834 #
number of cpu cycles simulated
+system.cpu.numCycles 549000668 #
number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu.contextSwitches 1 #
Number of context switches
-system.cpu.threadCycles 547808694 #
Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 538772486 #
Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 #
Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 412073 #
Number of times that the entire CPU went into an idle state and unscheduled
itself
-system.cpu.idleCycles 61249901 #
Number of cycles cpu's stages were not processed
-system.cpu.runCycles 496784933 #
Number of cycles cpu stages are processed.
-system.cpu.activity 89.024000 #
Percentage of cycles cpu is active
+system.cpu.timesIdled 412059 #
Number of times that the entire CPU went into an idle state and unscheduled
itself
+system.cpu.idleCycles 59486579 #
Number of cycles cpu's stages were not processed
+system.cpu.runCycles 489514089 #
Number of cycles cpu stages are processed.
+system.cpu.activity 89.164571 #
Percentage of cycles cpu is active
system.cpu.comLoads 114514042 #
Number of Load instructions committed
system.cpu.comStores 39451321 #
Number of Store instructions committed
system.cpu.comBranches 62547159 #
Number of Branches instructions committed
@@ -61,79 +61,79 @@
system.cpu.committedInsts 601856964 #
Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 #
Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 601856964 #
Number of Instructions Simulated (Total)
-system.cpu.cpi 0.927188 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.912178 #
CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value #
CPI: Total SMT-CPI
-system.cpu.cpi_total 0.927188 #
CPI: Total CPI of All Threads
-system.cpu.ipc 1.078529 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.912178 #
CPI: Total CPI of All Threads
+system.cpu.ipc 1.096277 #
IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value #
IPC: Total SMT-IPC
-system.cpu.ipc_total 1.078529 #
IPC: Total IPC of All Threads
-system.cpu.branch_predictor.lookups 90037625 #
Number of BP lookups
-system.cpu.branch_predictor.condPredicted 84897563 #
Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 39773148 #
Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 49497029 #
Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 39091844 #
Number of BTB hits
+system.cpu.ipc_total 1.096277 #
IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups 86959577 #
Number of BP lookups
+system.cpu.branch_predictor.condPredicted 82118654 #
Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 36581334 #
Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 45689066 #
Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 35726566 #
Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 #
Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 #
Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 78.978163 #
BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 41686827
# Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 48350798
# Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 541420411
# Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 78.195002 #
BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 38245021
# Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 48714556
# Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 540577865
# Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846
# Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 1005275257
# Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 1004432711
# Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162
# Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42
# Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204
# Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 257533113 #
Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 154627572 #
Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 38276366
# Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 1491795
# Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 39768161 #
Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 22779717 #
Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 63.580352 #
Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 411890550 #
Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards 255585026 #
Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 154582342 #
Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 35142167
# Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 1434180
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 36576347 #
Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 25971564 #
Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 58.477328 #
Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 411886396 #
Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 #
Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 #
Number of Divide Operations Executed
-system.cpu.stage0.idleCycles 210144173 #
Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 347890661 #
Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 62.342105 #
Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 246346046 #
Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 311688788 #
Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 55.854719 #
Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 214904658 #
Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 343130176 #
Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 61.489025 #
Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 446207500 #
Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 111827334 #
Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.039490 #
Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 210384695 #
Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 347650139 #
Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 62.299003 #
Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles 209828742 #
Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 339171926 #
Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 61.779875 #
Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 238624991 #
Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 310375677 #
Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 56.534663 #
Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 207052073 #
Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 341948595 #
Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 62.285643 #
Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 437467887 #
Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 111532781 #
Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.315600 #
Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 201947249 #
Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 347053419 #
Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 63.215482 #
Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 #
number of replacements
-system.cpu.icache.tagsinuse 726.393228 #
Cycle average of tags in use
-system.cpu.icache.total_refs 29077078 #
Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 852 #
Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 34128.025822 #
Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 728.259897 #
Cycle average of tags in use
+system.cpu.icache.total_refs 27985205 #
Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 855 #
Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 32731.233918 #
Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 726.393228 #
Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.354684 #
Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 29077078 #
number of ReadReq hits
-system.cpu.icache.demand_hits 29077078 #
number of demand (read+write) hits
-system.cpu.icache.overall_hits 29077078 #
number of overall hits
-system.cpu.icache.ReadReq_misses 1015 #
number of ReadReq misses
-system.cpu.icache.demand_misses 1015 #
number of demand (read+write) misses
-system.cpu.icache.overall_misses 1015 #
number of overall misses
-system.cpu.icache.ReadReq_miss_latency 56421500 #
number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 56421500 #
number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 56421500 #
number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 29078093 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 29078093 #
number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 29078093 #
number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000035 #
miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000035 #
miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000035 #
miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55587.684729
# average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55587.684729 #
average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55587.684729
# average overall miss latency
+system.cpu.icache.occ_blocks::0 728.259897 #
Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.355596 #
Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 27985205 #
number of ReadReq hits
+system.cpu.icache.demand_hits 27985205 #
number of demand (read+write) hits
+system.cpu.icache.overall_hits 27985205 #
number of overall hits
+system.cpu.icache.ReadReq_misses 1019 #
number of ReadReq misses
+system.cpu.icache.demand_misses 1019 #
number of demand (read+write) misses
+system.cpu.icache.overall_misses 1019 #
number of overall misses
+system.cpu.icache.ReadReq_miss_latency 56646500 #
number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 56646500 #
number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 56646500 #
number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 27986224 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 27986224 #
number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 27986224 #
number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000036 #
miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000036 #
miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000036 #
miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55590.284593
# average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55590.284593 #
average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55590.284593
# average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 43500
# number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
@@ -143,159 +143,159 @@
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.cache_copies 0 #
number of cache copies performed
system.cpu.icache.writebacks 0 #
number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 163 #
number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 163 #
number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 163 #
number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 852 #
number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 852 #
number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 852 #
number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits 164 #
number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 164 #
number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 164 #
number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 855 #
number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 855 #
number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 855 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 45615500
# number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 45615500
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 45615500
# number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 45774000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 45774000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 45774000
# number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 #
mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000029 #
mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000029 #
mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249
# average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249
# average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249
# average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000031 #
mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000031 #
mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105
# average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105
# average overall mshr miss latency
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