> On 2011-07-10 11:29:38, Ali Saidi wrote: > > src/cpu/o3/lsq_unit.hh, line 584 > > <http://reviews.m5sim.org/r/502/diff/3/?file=13288#file13288line584> > > > > Where does this get freed?
In the dynInst destructor. This is what's done for regular loads and stores too. It has to belong to the instruction and not an individual access since the same memory may be filled by two accesses and can't be freed in two pieces. I definitely agree that it wasn't straightforward finding where it gets deleted. > On 2011-07-10 11:29:38, Ali Saidi wrote: > > src/cpu/o3/lsq_unit.hh, line 594 > > <http://reviews.m5sim.org/r/502/diff/3/?file=13288#file13288line594> > > > > Is this you being careful or can a mem mapped ipr access actually split > > across two different operations? Doesn't really seem like it should need to > > because translation crossing a cache boundary shouldn't be an issue for a > > memory mapped ipr, but perhaps it's easier this way? Lastly should all this > > mm ipr code be in the .hh file? I think mostly being careful, but it's easy to avoid building that sort of restriction into the CPU especially since it doesn't apply for regular accesses. I'm not really happy having all that code in a .hh, but it technically is if it's in impl.hh too, and I don't want to chop holes in the middle of those functions if it doesn't really buy anything. I think that's an unfortunate side effect of how much we use templating in O3. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/502/#review1399 ----------------------------------------------------------- On 2011-07-03 03:36:00, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/502/ > ----------------------------------------------------------- > > (Updated 2011-07-03 03:36:00) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Implement memory mapped IPRs for O3. > > > Diffs > ----- > > src/cpu/o3/lsq_unit.hh 1b4b9c05ad2b > src/cpu/o3/lsq_unit_impl.hh 1b4b9c05ad2b > > Diff: http://reviews.m5sim.org/r/502/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
