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Ship it! I spotted two minor non-functional things that could be polished, but basically this looks fine. Thanks for the effort on fixing this. src/mem/cache/cache_impl.hh <http://reviews.m5sim.org/r/787/#comment1845> I think you can get rid of this assert since the new if clause covers that case. src/mem/cache/cache_impl.hh <http://reviews.m5sim.org/r/787/#comment1846> I'd change "we could get a copy from a lower level or main memory that isn't dirty and it might replace a dirty one in cache if the upper level happens to write back in the middle of a prefetch" to "we could get a stale copy from memory that might get used in place of the dirty one"... you're mentioning one specific symptom but I suspect that's not the only one, so the shorter comment should suffice. - Steve On 2011-07-13 14:41:49, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/787/ > ----------------------------------------------------------- > > (Updated 2011-07-13 14:41:49) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Mem: Fix issue with prefetches originating at non-L1 caches getting stale data > > Prefetch requests issued from the L2 or below wouldn't check if valid data is > present higher in the system. If a prefetch into the L2 occured at the same > time as writeback from a higher-level cache the dirty data could be replaced > in by unmodified data in memory. > > > Diffs > ----- > > src/mem/cache/cache_impl.hh 82ff928182c5 > > Diff: http://reviews.m5sim.org/r/787/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
