changeset a9eae846c229 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a9eae846c229
description:
ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
diffstat:
src/arch/arm/ArmSystem.py | 4 ++--
src/arch/arm/isa/insts/swap.isa | 14 ++++++++++++--
2 files changed, 14 insertions(+), 4 deletions(-)
diffs (47 lines):
diff -r 5e9530779f60 -r a9eae846c229 src/arch/arm/ArmSystem.py
--- a/src/arch/arm/ArmSystem.py Fri Jul 15 11:53:34 2011 -0500
+++ b/src/arch/arm/ArmSystem.py Fri Jul 15 11:53:34 2011 -0500
@@ -49,9 +49,9 @@
# 0x35 Implementor is '5' from "M5"
# 0x0 Variant
# 0xf Architecture from CPUID scheme
- # 0xf00 Primary part number
+ # 0xc00 Primary part number ("c" or higher implies ARM v7)
# 0x0 Revision
- midr_regval = Param.UInt32(0x350ff000, "MIDR value")
+ midr_regval = Param.UInt32(0x350fc000, "MIDR value")
boot_loader = Param.String("", "File that contains the boot loader code if
any")
boot_loader_mem = Param.PhysicalMemory(NULL,
"Memory object that boot loader is to be loaded
into")
diff -r 5e9530779f60 -r a9eae846c229 src/arch/arm/isa/insts/swap.isa
--- a/src/arch/arm/isa/insts/swap.isa Fri Jul 15 11:53:34 2011 -0500
+++ b/src/arch/arm/isa/insts/swap.isa Fri Jul 15 11:53:34 2011 -0500
@@ -71,8 +71,18 @@
decoder_output += newDecoder
exec_output += newExec
+ swpPreAccCode = '''
+ if (!((SCTLR)Sctlr).sw) {
+#if FULL_SYSTEM
+ return new UndefinedInstruction;
+#else
+ return new UndefinedInstruction(false, mnemonic);
+#endif
+ }
+ '''
+
SwapInst('swp', 'Swp', 'EA = Base;',
- 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);',
+ swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);',
'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignWord',
@@ -80,7 +90,7 @@
['IsStoreConditional']).emit()
SwapInst('swpb', 'Swpb', 'EA = Base;',
- 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
+ swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignByte',
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