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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- Fix bugs due to interaction between SEV instructions and O3 pipeline SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending. Diffs ----- src/arch/arm/faults.hh 7f49e6a176b8 src/arch/arm/faults.cc 7f49e6a176b8 src/arch/arm/interrupts.hh 7f49e6a176b8 src/arch/arm/isa/insts/misc.isa 7f49e6a176b8 src/arch/arm/isa/templates/pred.isa 7f49e6a176b8 src/arch/arm/isa_traits.hh 7f49e6a176b8 src/cpu/o3/commit_impl.hh 7f49e6a176b8 src/cpu/o3/cpu.hh 7f49e6a176b8 src/cpu/o3/thread_context_impl.hh 7f49e6a176b8 Diff: http://reviews.m5sim.org/r/807/diff Testing ------- Thanks, Ali _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
