Hey Korey, I was talking to Ali about these changes, and he said you'd had a good argument in the past for why this assert was correct and needs to stay in O3. Could you please explain your reason again? I think it went off when things were working like they're supposed to which is why I wanted to remove it, but I don't want to if it's really finding a problem.
Gabe On 07/11/11 05:02, Gabe Black wrote: > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/777/ > ----------------------------------------------------------- > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Don't assert that nothing is pending in the decoder at the start of a > cycle. > > The decoder clears out incoming instructions from fetch on a squash, but there > may be instructions on the wire incoming from fetch which don't get cleared. > Because the decoder is considered squashing, it doesn't actually process any > more instructions as they come in. The instructions that were on their way > would then sit in the "insts" list until the next cycle, tripping qn assert. > It's ok for them to be there in that case because the decoder will just ignore > them. Because "insts" is a queue and can't be scanned to verify that all > instructions left on it are squashed, this change simply gets rid of the > check. > > > Diffs > ----- > > src/cpu/o3/decode_impl.hh 9f3fedee88e2 > > Diff: http://reviews.m5sim.org/r/777/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
