changeset 081ce5ab92ca in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=081ce5ab92ca description: Stats: Update stats for the previous change.
diffstat: tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 4 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 10 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1055 ++++----- tests/long/10.linux-boot/ref/arm/linux/realview-o3/status | 2 +- 4 files changed, 527 insertions(+), 544 deletions(-) diffs (truncated from 1260 to 300 lines): diff -r 2e12a633d269 -r 081ce5ab92ca tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Sun Aug 07 15:41:07 2011 -0700 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Sun Aug 07 15:41:09 2011 -0700 @@ -15,7 +15,7 @@ flags_addr=0 gic_cpu_addr=0 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/dist/m5/system/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -501,7 +501,7 @@ [system.diskmem] type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 +file=/dist/m5/system/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff -r 2e12a633d269 -r 081ce5ab92ca tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Sun Aug 07 15:41:07 2011 -0700 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Sun Aug 07 15:41:09 2011 -0700 @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2011 13:16:08 -gem5 started Jul 10 2011 13:18:46 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 7 2011 09:26:50 +gem5 started Aug 7 2011 09:26:59 +gem5 executing on burrito command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 80755049500 because m5_exit instruction encountered +Exiting @ tick 80737865500 because m5_exit instruction encountered diff -r 2e12a633d269 -r 081ce5ab92ca tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Sun Aug 07 15:41:07 2011 -0700 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Sun Aug 07 15:41:09 2011 -0700 @@ -1,101 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080755 # Number of seconds simulated -sim_ticks 80755049500 # Number of ticks simulated +sim_seconds 0.080738 # Number of seconds simulated +sim_ticks 80737865500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42177 # Simulator instruction rate (inst/s) -host_tick_rate 65656485 # Simulator tick rate (ticks/s) -host_mem_usage 388872 # Number of bytes of host memory used -host_seconds 1229.96 # Real time elapsed on the host -sim_insts 51876527 # Number of instructions simulated -system.l2c.replacements 94951 # number of replacements -system.l2c.tagsinuse 38190.664860 # Cycle average of tags in use -system.l2c.total_refs 1060547 # Total number of references to valid blocks. -system.l2c.sampled_refs 127388 # Sample count of references to valid blocks. -system.l2c.avg_refs 8.325329 # Average number of references to valid blocks. +host_inst_rate 39525 # Simulator instruction rate (inst/s) +host_tick_rate 61513284 # Simulator tick rate (ticks/s) +host_mem_usage 368852 # Number of bytes of host memory used +host_seconds 1312.53 # Real time elapsed on the host +sim_insts 51877265 # Number of instructions simulated +system.l2c.replacements 94990 # number of replacements +system.l2c.tagsinuse 38163.791653 # Cycle average of tags in use +system.l2c.total_refs 1058289 # Total number of references to valid blocks. +system.l2c.sampled_refs 127415 # Sample count of references to valid blocks. +system.l2c.avg_refs 8.305843 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6775.267374 # Average occupied blocks per context -system.l2c.occ_blocks::1 31415.397486 # Average occupied blocks per context -system.l2c.occ_percent::0 0.103382 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.479361 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 745613 # number of ReadReq hits -system.l2c.ReadReq_hits::1 120260 # number of ReadReq hits -system.l2c.ReadReq_hits::total 865873 # number of ReadReq hits -system.l2c.Writeback_hits::0 435187 # number of Writeback hits -system.l2c.Writeback_hits::total 435187 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 60895 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60895 # number of ReadExReq hits -system.l2c.demand_hits::0 806508 # number of demand (read+write) hits -system.l2c.demand_hits::1 120260 # number of demand (read+write) hits -system.l2c.demand_hits::total 926768 # number of demand (read+write) hits -system.l2c.overall_hits::0 806508 # number of overall hits -system.l2c.overall_hits::1 120260 # number of overall hits -system.l2c.overall_hits::total 926768 # number of overall hits -system.l2c.ReadReq_misses::0 21201 # number of ReadReq misses -system.l2c.ReadReq_misses::1 103 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21304 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1679 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1679 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 107626 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107626 # number of ReadExReq misses -system.l2c.demand_misses::0 128827 # number of demand (read+write) misses -system.l2c.demand_misses::1 103 # number of demand (read+write) misses -system.l2c.demand_misses::total 128930 # number of demand (read+write) misses -system.l2c.overall_misses::0 128827 # number of overall misses -system.l2c.overall_misses::1 103 # number of overall misses -system.l2c.overall_misses::total 128930 # number of overall misses -system.l2c.ReadReq_miss_latency 1113607000 # number of ReadReq miss cycles +system.l2c.occ_blocks::0 6719.704145 # Average occupied blocks per context +system.l2c.occ_blocks::1 31444.087508 # Average occupied blocks per context +system.l2c.occ_percent::0 0.102535 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.479799 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 746044 # number of ReadReq hits +system.l2c.ReadReq_hits::1 122406 # number of ReadReq hits +system.l2c.ReadReq_hits::total 868450 # number of ReadReq hits +system.l2c.Writeback_hits::0 435356 # number of Writeback hits +system.l2c.Writeback_hits::total 435356 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 23 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 60912 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60912 # number of ReadExReq hits +system.l2c.demand_hits::0 806956 # number of demand (read+write) hits +system.l2c.demand_hits::1 122406 # number of demand (read+write) hits +system.l2c.demand_hits::total 929362 # number of demand (read+write) hits +system.l2c.overall_hits::0 806956 # number of overall hits +system.l2c.overall_hits::1 122406 # number of overall hits +system.l2c.overall_hits::total 929362 # number of overall hits +system.l2c.ReadReq_misses::0 21087 # number of ReadReq misses +system.l2c.ReadReq_misses::1 100 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21187 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1678 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1678 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 107779 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107779 # number of ReadExReq misses +system.l2c.demand_misses::0 128866 # number of demand (read+write) misses +system.l2c.demand_misses::1 100 # number of demand (read+write) misses +system.l2c.demand_misses::total 128966 # number of demand (read+write) misses +system.l2c.overall_misses::0 128866 # number of overall misses +system.l2c.overall_misses::1 100 # number of overall misses +system.l2c.overall_misses::total 128966 # number of overall misses +system.l2c.ReadReq_miss_latency 1107503500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 5645255000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 6758862000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 6758862000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 766814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 120363 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 887177 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 435187 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 435187 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1705 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1705 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 168521 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168521 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 935335 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 120363 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1055698 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 935335 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 120363 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1055698 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027648 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000856 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028504 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.984751 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.638650 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.137734 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000856 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.138589 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.137734 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000856 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.138589 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52526.154427 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 10811718.446602 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 10864244.601029 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 433.889220 # average UpgradeReq miss latency +system.l2c.ReadExReq_miss_latency 5653158500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 6760662000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 6760662000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 767131 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 122506 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 889637 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 435356 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 435356 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1701 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1701 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 168691 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168691 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 935822 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 122506 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1058328 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 935822 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 122506 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1058328 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027488 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000816 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028304 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.986479 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.638914 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.137704 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000816 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.138520 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.137704 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000816 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.138520 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52520.676246 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 11075035 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 11127555.676246 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 434.147795 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52452.520766 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52451.391273 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52464.638624 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 65620019.417476 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 65672484.056100 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52464.638624 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 65620019.417476 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 65672484.056100 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52462.728726 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 67606620 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 67659082.728726 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52462.728726 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 67606620 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 67659082.728726 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,44 +100,44 @@ system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 87785 # number of writebacks -system.l2c.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 53 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 53 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 21251 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1679 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 107626 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 128877 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 128877 # number of overall MSHR misses +system.l2c.writebacks 87808 # number of writebacks +system.l2c.ReadReq_mshr_hits 58 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 58 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 58 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 21129 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1678 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 107779 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 128908 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 128908 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 851149000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 67161500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4306288000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 5157437000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 5157437000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 28946617000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 748511947 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 29695128947 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027713 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.176558 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.204271 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.984751 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 846277000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 67121500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4312433500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 5158710500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 5158710500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 28946618500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 748700947 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29695319447 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.172473 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.200016 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.986479 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.638650 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.638914 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.137787 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.070736 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.208523 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.137787 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.070736 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.208523 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40052.185779 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.893389 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40011.595711 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40018.288756 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40018.288756 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.137748 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.052259 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.190007 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.137748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.052259 # mshr miss rate for overall accesses _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
