changeset cf2eb466f74d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=cf2eb466f74d description: Stats: Update stats for the end of macroop O3 fix.
diffstat: tests/long/20.parser/ref/x86/linux/o3-timing/simout | 8 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 692 ++++++++-------- 2 files changed, 350 insertions(+), 350 deletions(-) diffs (truncated from 821 to 300 lines): diff -r 6ee3a2359fcb -r cf2eb466f74d tests/long/20.parser/ref/x86/linux/o3-timing/simout --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout Tue Aug 09 11:30:43 2011 -0700 +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout Tue Aug 09 11:31:48 2011 -0700 @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 29 2011 20:26:37 -gem5 started Jul 29 2011 20:48:01 -gem5 executing on chips +gem5 compiled Aug 9 2011 03:42:03 +gem5 started Aug 9 2011 03:42:10 +gem5 executing on burrito command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -77,4 +77,4 @@ about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 589091030500 because target called exit() +Exiting @ tick 589090675500 because target called exit() diff -r 6ee3a2359fcb -r cf2eb466f74d tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt Tue Aug 09 11:30:43 2011 -0700 +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt Tue Aug 09 11:31:48 2011 -0700 @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.589091 # Number of seconds simulated -sim_ticks 589091030500 # Number of ticks simulated +sim_ticks 589090675500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49258 # Simulator instruction rate (inst/s) -host_tick_rate 18978173 # Simulator tick rate (ticks/s) -host_mem_usage 295880 # Number of bytes of host memory used -host_seconds 31040.45 # Real time elapsed on the host +host_inst_rate 112556 # Simulator instruction rate (inst/s) +host_tick_rate 43365548 # Simulator tick rate (ticks/s) +host_mem_usage 283452 # Number of bytes of host memory used +host_seconds 13584.30 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1178182062 # number of cpu cycles simulated +system.cpu.numCycles 1178181352 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 273761265 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 273761265 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16674451 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 263536276 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 242767541 # Number of BTB hits +system.cpu.BPredUnit.lookups 273757623 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 273757623 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16675490 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 263549341 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 242783389 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 225401739 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1479491237 # Number of instructions fetch has processed -system.cpu.fetch.Branches 273761265 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 242767541 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 481293479 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 151906639 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 310358481 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 81567 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 542630 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 210837285 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3978525 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1150020807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.401549 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.263992 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 225396443 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1479442245 # Number of instructions fetch has processed +system.cpu.fetch.Branches 273757623 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 242783389 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 481291877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 151896782 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 310377272 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 81634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 545852 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 210829674 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3979750 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1150024812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.401504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.263970 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 673309579 58.55% 58.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 35910144 3.12% 61.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 42110719 3.66% 65.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 37429485 3.25% 68.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23065553 2.01% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42484640 3.69% 74.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 50557962 4.40% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39843815 3.46% 82.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 205308910 17.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 673316869 58.55% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35917007 3.12% 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 42114186 3.66% 65.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 37411519 3.25% 68.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23065398 2.01% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42495758 3.70% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 50561789 4.40% 78.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39840695 3.46% 82.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 205301591 17.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1150020807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.232359 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.255741 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 295424078 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258223028 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403450354 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 60580436 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 132342911 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2687346681 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 53 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 132342911 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 338937785 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65386701 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 418304100 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 195020519 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2631430164 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 26828 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 78975062 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 100019003 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2450674734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6174029240 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6173774386 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 254854 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1150024812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.232356 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.255700 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 295420546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258244912 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403447600 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 60580020 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 132331734 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2687300913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 91 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 132331734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 338940336 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65400772 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26776 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 418290403 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 195034791 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2631340951 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 26774 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 78955690 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 100051719 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2450677508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6173942616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6173688000 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 254616 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1023375707 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3026 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3017 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 414859907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 629524588 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 242192886 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 419436220 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 160455315 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2509631781 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14404 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1981481071 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1143998 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979086387 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1684803176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13851 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1150020807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.722996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.682483 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1023378481 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2754 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2753 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 414898876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 629493820 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 242177233 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 419306187 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 160446985 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2509527923 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14190 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1981485424 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1148160 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978984128 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1684574275 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13637 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1150024812 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.722994 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.682548 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 371533826 32.31% 32.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 234816384 20.42% 52.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 195375201 16.99% 69.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 160336940 13.94% 83.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104083103 9.05% 92.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 52438845 4.56% 97.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24322326 2.11% 99.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6470584 0.56% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 643598 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 371543440 32.31% 32.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 234819664 20.42% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 195395940 16.99% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 160294242 13.94% 83.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104067895 9.05% 92.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 52467261 4.56% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24318535 2.11% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6470621 0.56% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 647214 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1150020807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1150024812 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2000225 14.58% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1998808 14.58% 14.58% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 14.58% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 14.58% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.58% # attempts to use FU when none available @@ -134,119 +134,119 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.58% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.58% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9217501 67.18% 81.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2502434 18.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9206664 67.16% 81.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2503442 18.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2582217 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1339393426 67.60% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 465725544 23.50% 91.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173779884 8.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2582418 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1339368351 67.59% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 465740046 23.50% 91.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173794609 8.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
