changeset 479b186a4652 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=479b186a4652
description:
O3: When squashing, restore the macroop that should be used for
fetching.
diffstat:
src/cpu/o3/comm.hh | 1 +
src/cpu/o3/decode_impl.hh | 1 +
src/cpu/o3/fetch.hh | 10 ++++++----
src/cpu/o3/fetch_impl.hh | 18 ++++++++++++------
4 files changed, 20 insertions(+), 10 deletions(-)
diffs (116 lines):
diff -r f1fc7102c970 -r 479b186a4652 src/cpu/o3/comm.hh
--- a/src/cpu/o3/comm.hh Sun Aug 14 04:08:14 2011 -0700
+++ b/src/cpu/o3/comm.hh Sun Aug 14 17:41:34 2011 -0700
@@ -135,6 +135,7 @@
bool branchTaken;
Addr mispredPC;
TheISA::PCState nextPC;
+ DynInstPtr squashInst;
unsigned branchCount;
};
diff -r f1fc7102c970 -r 479b186a4652 src/cpu/o3/decode_impl.hh
--- a/src/cpu/o3/decode_impl.hh Sun Aug 14 04:08:14 2011 -0700
+++ b/src/cpu/o3/decode_impl.hh Sun Aug 14 17:41:34 2011 -0700
@@ -280,6 +280,7 @@
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
+ toFetch->decodeInfo[tid].squashInst = inst;
InstSeqNum squash_seq_num = inst->seqNum;
diff -r f1fc7102c970 -r 479b186a4652 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Sun Aug 14 04:08:14 2011 -0700
+++ b/src/cpu/o3/fetch.hh Sun Aug 14 17:41:34 2011 -0700
@@ -332,13 +332,15 @@
}
/** Squashes a specific thread and resets the PC. */
- inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
+ inline void doSquash(const TheISA::PCState &newPC,
+ const DynInstPtr squashInst, ThreadID tid);
/** Squashes a specific thread and resets the PC. Also tells the CPU to
* remove any instructions between fetch and decode that should be
sqaushed.
*/
void squashFromDecode(const TheISA::PCState &newPC,
- const InstSeqNum &seq_num, ThreadID tid);
+ const DynInstPtr squashInst,
+ const InstSeqNum seq_num, ThreadID tid);
/** Checks if a thread is stalled. */
bool checkStall(ThreadID tid) const;
@@ -352,8 +354,8 @@
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
- void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
- DynInstPtr &squashInst, ThreadID tid);
+ void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
+ DynInstPtr squashInst, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.
diff -r f1fc7102c970 -r 479b186a4652 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sun Aug 14 04:08:14 2011 -0700
+++ b/src/cpu/o3/fetch_impl.hh Sun Aug 14 17:41:34 2011 -0700
@@ -746,14 +746,18 @@
template <class Impl>
inline void
-DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
+DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
+ const DynInstPtr squashInst, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
tid, newPC);
pc[tid] = newPC;
fetchOffset[tid] = 0;
- macroop[tid] = NULL;
+ if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
+ macroop[tid] = squashInst->macroop;
+ else
+ macroop[tid] = NULL;
predecoder.reset();
// Clear the icache miss if it's outstanding.
@@ -786,11 +790,12 @@
template<class Impl>
void
DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
- const InstSeqNum &seq_num, ThreadID tid)
+ const DynInstPtr squashInst,
+ const InstSeqNum seq_num, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
- doSquash(newPC, tid);
+ doSquash(newPC, squashInst, tid);
// Tell the CPU to remove any instructions that are in flight between
// fetch and decode.
@@ -866,12 +871,12 @@
template <class Impl>
void
DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
- const InstSeqNum &seq_num, DynInstPtr &squashInst,
+ const InstSeqNum seq_num, DynInstPtr squashInst,
ThreadID tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
- doSquash(newPC, tid);
+ doSquash(newPC, squashInst, tid);
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid);
@@ -1052,6 +1057,7 @@
DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
+ fromDecode->decodeInfo[tid].squashInst,
fromDecode->decodeInfo[tid].doneSeqNum,
tid);
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