changeset a508c2d92d63 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a508c2d92d63
description:
ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
diffstat:
src/dev/arm/RealView.py | 9 +
src/dev/arm/SConscript | 1 +
src/dev/arm/gic.cc | 2 +
src/dev/arm/timer_cpulocal.cc | 440 ++++++++++++++++++++++++++++++++++++++++++
src/dev/arm/timer_cpulocal.hh | 199 ++++++++++++++++++
5 files changed, 651 insertions(+), 0 deletions(-)
diffs (truncated from 703 to 300 lines):
diff -r 426a06ee7274 -r a508c2d92d63 src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py Fri Aug 19 15:08:05 2011 -0500
+++ b/src/dev/arm/RealView.py Fri Aug 19 15:08:05 2011 -0500
@@ -108,6 +108,13 @@
clock1 = Param.Clock('1MHz', "Clock speed of the input")
amba_id = 0x00141804
+class CpuLocalTimer(BasicPioDevice):
+ type = 'CpuLocalTimer'
+ gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+ int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
+ int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to
GIC")
+ clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
+
class Pl050(AmbaIntDevice):
type = 'Pl050'
vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer
display")
@@ -134,6 +141,7 @@
gic = Gic()
timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
+ local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
pio_addr=0x1f000600)
clcd = Pl111(pio_addr=0x10020000, int_num=55)
kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
@@ -170,6 +178,7 @@
self.gic.pio = bus.port
self.l2x0_fake.pio = bus.port
self.a9scu.pio = bus.port
+ self.local_cpu_timer.pio = bus.port
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
diff -r 426a06ee7274 -r a508c2d92d63 src/dev/arm/SConscript
--- a/src/dev/arm/SConscript Fri Aug 19 15:08:05 2011 -0500
+++ b/src/dev/arm/SConscript Fri Aug 19 15:08:05 2011 -0500
@@ -52,6 +52,7 @@
Source('timer_sp804.cc')
Source('rv_ctrl.cc')
Source('realview.cc')
+ Source('timer_cpulocal.cc')
DebugFlag('AMBA')
DebugFlag('PL111')
diff -r 426a06ee7274 -r a508c2d92d63 src/dev/arm/gic.cc
--- a/src/dev/arm/gic.cc Fri Aug 19 15:08:05 2011 -0500
+++ b/src/dev/arm/gic.cc Fri Aug 19 15:08:05 2011 -0500
@@ -679,6 +679,8 @@
void
Gic::sendPPInt(uint32_t num, uint32_t cpu)
{
+ DPRINTF(Interrupt, "Received Interrupt number %d, cpuTarget %#x: \n",
+ num, cpu);
cpuPpiPending[cpu] |= 1 << (num - SGI_MAX);
updateIntState(intNumToWord(num));
}
diff -r 426a06ee7274 -r a508c2d92d63 src/dev/arm/timer_cpulocal.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/arm/timer_cpulocal.cc Fri Aug 19 15:08:05 2011 -0500
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2010-2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Geoffrey Blake
+ */
+
+#include "base/intmath.hh"
+#include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/Timer.hh"
+#include "dev/arm/gic.hh"
+#include "dev/arm/timer_cpulocal.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+CpuLocalTimer::CpuLocalTimer(Params *p)
+ : BasicPioDevice(p), gic(p->gic)
+{
+ // Initialize the timer registers for each per cpu timer
+ for (int i = 0; i < CPU_MAX; i++) {
+ std::stringstream oss;
+ oss << name() << ".timer" << i;
+ localTimer[i]._name = oss.str();
+ localTimer[i].parent = this;
+ localTimer[i].intNumTimer = p->int_num_timer;
+ localTimer[i].intNumWatchdog = p->int_num_watchdog;
+ localTimer[i].clock = p->clock;
+ localTimer[i].cpuNum = i;
+ }
+ pioSize = 0x38;
+}
+
+CpuLocalTimer::Timer::Timer()
+ : timerControl(0x0), watchdogControl(0x0), rawIntTimer(false),
rawIntWatchdog(false),
+ rawResetWatchdog(false), watchdogDisableReg(0x0),
pendingIntTimer(false), pendingIntWatchdog(false),
+ timerLoadValue(0x0), watchdogLoadValue(0x0), timerZeroEvent(this),
watchdogZeroEvent(this)
+{
+}
+
+Tick
+CpuLocalTimer::read(PacketPtr pkt)
+{
+ assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+ assert(pkt->getSize() == 4);
+ Addr daddr = pkt->getAddr() - pioAddr;
+ pkt->allocate();
+ int cpu_id = pkt->req->contextId();
+ DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
+ assert(cpu_id >= 0);
+ assert(cpu_id < CPU_MAX);
+
+ if (daddr < Timer::Size)
+ localTimer[cpu_id].read(pkt, daddr);
+ else
+ panic("Tried to read CpuLocalTimer at offset %#x that doesn't
exist\n", daddr);
+ pkt->makeAtomicResponse();
+ return pioDelay;
+}
+
+
+void
+CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr)
+{
+ DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
+ Tick time;
+
+ switch(daddr) {
+ case TimerLoadReg:
+ pkt->set<uint32_t>(timerLoadValue);
+ break;
+ case TimerCounterReg:
+ DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n",
+ timerZeroEvent.when(), clock, timerControl.prescalar);
+ time = timerZeroEvent.when() - curTick();
+ time = time / clock / power(16, timerControl.prescalar);
+ DPRINTF(Timer, "-- returning counter at %d\n", time);
+ pkt->set<uint32_t>(time);
+ break;
+ case TimerControlReg:
+ pkt->set<uint32_t>(timerControl);
+ break;
+ case TimerIntStatusReg:
+ pkt->set<uint32_t>(rawIntTimer);
+ break;
+ case WatchdogLoadReg:
+ pkt->set<uint32_t>(watchdogLoadValue);
+ break;
+ case WatchdogCounterReg:
+ DPRINTF(Timer, "Event schedule for watchdog %d, clock=%d,
prescale=%d\n",
+ watchdogZeroEvent.when(), clock, watchdogControl.prescalar);
+ time = watchdogZeroEvent.when() - curTick();
+ time = time / clock / power(16, watchdogControl.prescalar);
+ DPRINTF(Timer, "-- returning counter at %d\n", time);
+ pkt->set<uint32_t>(time);
+ break;
+ case WatchdogControlReg:
+ pkt->set<uint32_t>(watchdogControl);
+ break;
+ case WatchdogIntStatusReg:
+ pkt->set<uint32_t>(rawIntWatchdog);
+ break;
+ case WatchdogResetStatusReg:
+ pkt->set<uint32_t>(rawResetWatchdog);
+ break;
+ case WatchdogDisableReg:
+ panic("Tried to read from WatchdogDisableRegister\n");
+ break;
+ default:
+ panic("Tried to read CpuLocalTimer at offset %#x\n", daddr);
+ break;
+ }
+}
+
+Tick
+CpuLocalTimer::write(PacketPtr pkt)
+{
+ assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+ assert(pkt->getSize() == 4);
+ Addr daddr = pkt->getAddr() - pioAddr;
+ pkt->allocate();
+ int cpu_id = pkt->req->contextId();
+ DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
+ assert(cpu_id >= 0);
+ assert(cpu_id < CPU_MAX);
+
+ if (daddr < Timer::Size)
+ localTimer[cpu_id].write(pkt, daddr);
+ else
+ panic("Tried to write CpuLocalTimer at offset %#x that doesn't
exist\n", daddr);
+ pkt->makeAtomicResponse();
+ return pioDelay;
+}
+
+void
+CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr)
+{
+ DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
+ bool old_enable;
+ bool old_wd_mode;
+ uint32_t old_val;
+
+ switch (daddr) {
+ case TimerLoadReg:
+ // Writing to this register also resets the counter register and
+ // starts decrementing if the counter is enabled.
+ timerLoadValue = pkt->get<uint32_t>();
+ restartTimerCounter(timerLoadValue);
+ break;
+ case TimerCounterReg:
+ // Can be written, doesn't start counting unless the timer is enabled
+ restartTimerCounter(pkt->get<uint32_t>());
+ break;
+ case TimerControlReg:
+ old_enable = timerControl.enable;
+ timerControl = pkt->get<uint32_t>();
+ if ((old_enable == 0) && timerControl.enable)
+ restartTimerCounter(timerLoadValue);
+ break;
+ case TimerIntStatusReg:
+ rawIntTimer = false;
+ if (pendingIntTimer) {
+ pendingIntTimer = false;
+ DPRINTF(Timer, "Clearing interrupt\n");
+ }
+ break;
+ case WatchdogLoadReg:
+ watchdogLoadValue = pkt->get<uint32_t>();
+ restartWatchdogCounter(watchdogLoadValue);
+ break;
+ case WatchdogCounterReg:
+ // Can't be written when in watchdog mode, but can in timer mode
+ if (!watchdogControl.watchdogMode) {
+ restartWatchdogCounter(pkt->get<uint32_t>());
+ }
+ break;
+ case WatchdogControlReg:
+ old_enable = watchdogControl.enable;
+ old_wd_mode = watchdogControl.watchdogMode;
+ watchdogControl = pkt->get<uint32_t>();
+ if ((old_enable == 0) && watchdogControl.enable)
+ restartWatchdogCounter(watchdogLoadValue);
+ // cannot disable watchdog using control register
+ if ((old_wd_mode == 1) && watchdogControl.watchdogMode == 0)
+ watchdogControl.watchdogMode = 1;
+ break;
+ case WatchdogIntStatusReg:
+ rawIntWatchdog = false;
+ if (pendingIntWatchdog) {
+ pendingIntWatchdog = false;
+ DPRINTF(Timer, "Clearing watchdog interrupt\n");
+ }
+ break;
+ case WatchdogResetStatusReg:
+ rawResetWatchdog = false;
+ DPRINTF(Timer, "Clearing watchdog reset flag\n");
+ break;
+ case WatchdogDisableReg:
+ old_val = watchdogDisableReg;
+ watchdogDisableReg = pkt->get<uint32_t>();
+ // if this sequence is observed, turn off watchdog mode
+ if (old_val == 0x12345678 && watchdogDisableReg == 0x87654321)
+ watchdogControl.watchdogMode = 0;
+ break;
+ default:
+ panic("Tried to write CpuLocalTimer timer at offset %#x\n", daddr);
+ break;
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