changeset 12420b96b364 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=12420b96b364
description:
LSQ: Fix a few issues with the storeset predictor.
Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse
order.
2. The flag indicating that a barrier is inflight was never cleared when
the barrier was squashed instead of committed. This made all load
insts
dependent on a non-existent barrier in-flight.
diffstat:
src/cpu/o3/mem_dep_unit_impl.hh | 13 +++++++++----
1 files changed, 9 insertions(+), 4 deletions(-)
diffs (43 lines):
diff -r 57c96df312a1 -r 12420b96b364 src/cpu/o3/mem_dep_unit_impl.hh
--- a/src/cpu/o3/mem_dep_unit_impl.hh Fri Aug 19 15:08:05 2011 -0500
+++ b/src/cpu/o3/mem_dep_unit_impl.hh Fri Aug 19 15:08:05 2011 -0500
@@ -405,15 +405,14 @@
completed(inst);
InstSeqNum barr_sn = inst->seqNum;
-
+ DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
+ inst->seqNum);
if (inst->isMemBarrier()) {
- assert(loadBarrier && storeBarrier);
if (loadBarrierSN == barr_sn)
loadBarrier = false;
if (storeBarrierSN == barr_sn)
storeBarrier = false;
} else if (inst->isWriteBarrier()) {
- assert(storeBarrier);
if (storeBarrierSN == barr_sn)
storeBarrier = false;
}
@@ -480,6 +479,12 @@
DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
(*squash_it)->seqNum);
+ if ((*squash_it)->seqNum == loadBarrierSN)
+ loadBarrier = false;
+
+ if ((*squash_it)->seqNum == storeBarrierSN)
+ storeBarrier = false;
+
hash_it = memDepHash.find((*squash_it)->seqNum);
assert(hash_it != memDepHash.end());
@@ -509,7 +514,7 @@
" load: %#x, store: %#x\n", violating_load->instAddr(),
store_inst->instAddr());
// Tell the memory dependence unit of the violation.
- depPred.violation(violating_load->instAddr(), store_inst->instAddr());
+ depPred.violation(store_inst->instAddr(), violating_load->instAddr());
}
template <class MemDepPred, class Impl>
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