changeset 684ea9e5cd96 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=684ea9e5cd96 description: O3: Update stats for LSQ changes.
diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 742 +- tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 6 +- tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 760 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 6 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 739 +- tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 6 +- tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 724 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 14 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2290 ++++---- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1092 ++-- tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 24 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 12 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1067 ++-- tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal | 0 tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini | 6 +- tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout | 10 +- tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1167 ++-- tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 6 +- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 783 +- tests/long/10.mcf/ref/x86/linux/o3-timing/simout | 7 +- tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 726 +- tests/long/20.parser/ref/arm/linux/o3-timing/simout | 6 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 818 +- tests/long/20.parser/ref/x86/linux/o3-timing/config.ini | 4 +- tests/long/20.parser/ref/x86/linux/o3-timing/simout | 28 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 754 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 730 +- tests/long/30.eon/ref/arm/linux/o3-timing/simout | 6 +- tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt | 727 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 670 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 6 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 781 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 786 +- tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini | 2 +- tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 10 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 800 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 774 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/simout | 6 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 793 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 754 +- tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 8 +- tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 748 +- tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 6 +- tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 710 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 6 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 442 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 6 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 579 +- tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 6 +- tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 514 +- tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 6 +- tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 534 +- tests/quick/00.hello/ref/power/linux/o3-timing/simout | 6 +- tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 524 +- tests/quick/00.hello/ref/x86/linux/o3-timing/simout | 6 +- tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 528 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 6 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 756 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 6 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 414 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 50 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 2528 +++++----- 71 files changed, 13569 insertions(+), 13534 deletions(-) diffs (truncated from 32784 to 300 lines): diff -r a9c0d2ab490a -r 684ea9e5cd96 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Fri Aug 19 15:08:05 2011 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Fri Aug 19 15:08:06 2011 -0500 @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 16:09:24 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 18:05:21 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145300717500 because target called exit() +Exiting @ tick 145175788500 because target called exit() diff -r a9c0d2ab490a -r 684ea9e5cd96 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Fri Aug 19 15:08:05 2011 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Fri Aug 19 15:08:06 2011 -0500 @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145301 # Number of seconds simulated -sim_ticks 145300717500 # Number of ticks simulated +sim_seconds 0.145176 # Number of seconds simulated +sim_ticks 145175788500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109615 # Simulator instruction rate (inst/s) -host_tick_rate 28162171 # Simulator tick rate (ticks/s) -host_mem_usage 246532 # Number of bytes of host memory used -host_seconds 5159.43 # Real time elapsed on the host +host_inst_rate 116167 # Simulator instruction rate (inst/s) +host_tick_rate 29819633 # Simulator tick rate (ticks/s) +host_mem_usage 246468 # Number of bytes of host memory used +host_seconds 4868.46 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125840781 # DTB read hits -system.cpu.dtb.read_misses 26740 # DTB read misses +system.cpu.dtb.read_hits 125726238 # DTB read hits +system.cpu.dtb.read_misses 26702 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125867521 # DTB read accesses -system.cpu.dtb.write_hits 41455603 # DTB write hits -system.cpu.dtb.write_misses 32148 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41487751 # DTB write accesses -system.cpu.dtb.data_hits 167296384 # DTB hits -system.cpu.dtb.data_misses 58888 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167355272 # DTB accesses -system.cpu.itb.fetch_hits 71694847 # ITB hits +system.cpu.dtb.read_accesses 125752940 # DTB read accesses +system.cpu.dtb.write_hits 41507366 # DTB write hits +system.cpu.dtb.write_misses 32028 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 41539394 # DTB write accesses +system.cpu.dtb.data_hits 167233604 # DTB hits +system.cpu.dtb.data_misses 58730 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 167292334 # DTB accesses +system.cpu.itb.fetch_hits 71588816 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71694887 # ITB accesses +system.cpu.itb.fetch_accesses 71588856 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290601436 # number of cpu cycles simulated +system.cpu.numCycles 290351578 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits +system.cpu.BPredUnit.lookups 82068439 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75472139 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4139210 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77758293 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69764860 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed -system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1965418 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74381248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 740847057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 82068439 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71730278 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139388095 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17359106 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 63481916 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 71588816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1228525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290282404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.552160 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 150894309 51.98% 51.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11757724 4.05% 56.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15902063 5.48% 61.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15874475 5.47% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13293221 4.58% 71.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15622251 5.38% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6768599 2.33% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3592047 1.24% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56577715 19.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290282404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.282652 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.551552 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90540829 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 49762589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 127167334 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9782311 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13029341 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4494723 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 873 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 729210837 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3260 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 13029341 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98854754 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12652695 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 558 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123369042 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42376014 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 715226972 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32893526 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4012041 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 545137745 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 939207717 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 939205613 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2104 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 81282856 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 36 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 82693608 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131825687 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43890067 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17591169 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7047053 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 644543109 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 621562613 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 380292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77712656 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42125820 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 290282404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.141234 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.879500 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 70571105 24.31% 24.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 58751148 20.24% 44.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 55824387 19.23% 63.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31456534 10.84% 74.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 33062190 11.39% 86.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24005083 8.27% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12272709 4.23% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3831324 1.32% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 507924 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290282404 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4555010 86.10% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 57 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
