changeset 7ab22a73bda1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7ab22a73bda1 description: StoreSet: Update stats for store-set clearing
diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini | 3 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 758 +- tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini | 3 +- tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 10 +- tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 754 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini | 3 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 751 +- tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini | 3 +- tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 10 +- tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 746 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 2 + tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 8 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2154 +++++----- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 1 + tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 8 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1078 ++-- tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 1 + tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 8 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1083 ++-- tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini | 7 +- tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout | 12 +- tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1224 ++-- tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini | 5 +- tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 10 +- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 774 +- tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini | 5 +- tests/long/10.mcf/ref/x86/linux/o3-timing/simout | 10 +- tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 728 +- tests/long/20.parser/ref/arm/linux/o3-timing/config.ini | 5 +- tests/long/20.parser/ref/arm/linux/o3-timing/simout | 10 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 814 +- tests/long/20.parser/ref/x86/linux/o3-timing/config.ini | 1 + tests/long/20.parser/ref/x86/linux/o3-timing/simout | 28 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 768 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini | 3 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 752 +- tests/long/30.eon/ref/arm/linux/o3-timing/config.ini | 3 +- tests/long/30.eon/ref/arm/linux/o3-timing/simout | 10 +- tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt | 754 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini | 3 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 696 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini | 3 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 10 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 796 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini | 3 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 792 +- tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini | 1 + tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 8 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 816 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 3 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 768 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini | 3 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/simout | 10 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 797 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini | 3 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 12 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 746 +- tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini | 3 +- tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 10 +- tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 740 +- tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini | 3 +- tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 12 +- tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 734 +- 69 files changed, 10206 insertions(+), 10133 deletions(-) diffs (truncated from 24116 to 300 lines): diff -r f9a495adafd9 -r 7ab22a73bda1 tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Fri Aug 19 15:08:07 2011 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Fri Aug 19 15:08:08 2011 -0500 @@ -102,6 +102,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff -r f9a495adafd9 -r 7ab22a73bda1 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Fri Aug 19 15:08:07 2011 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Fri Aug 19 15:08:08 2011 -0500 @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 18:05:21 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:50:17 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -39,4 +41,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145175788500 because target called exit() +Exiting @ tick 145301847500 because target called exit() diff -r f9a495adafd9 -r 7ab22a73bda1 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Fri Aug 19 15:08:07 2011 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Fri Aug 19 15:08:08 2011 -0500 @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145176 # Number of seconds simulated -sim_ticks 145175788500 # Number of ticks simulated +sim_seconds 0.145302 # Number of seconds simulated +sim_ticks 145301847500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116167 # Simulator instruction rate (inst/s) -host_tick_rate 29819633 # Simulator tick rate (ticks/s) -host_mem_usage 246468 # Number of bytes of host memory used -host_seconds 4868.46 # Real time elapsed on the host +host_inst_rate 168398 # Simulator instruction rate (inst/s) +host_tick_rate 43264868 # Simulator tick rate (ticks/s) +host_mem_usage 252140 # Number of bytes of host memory used +host_seconds 3358.43 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125726238 # DTB read hits -system.cpu.dtb.read_misses 26702 # DTB read misses +system.cpu.dtb.read_hits 125931819 # DTB read hits +system.cpu.dtb.read_misses 26714 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125752940 # DTB read accesses -system.cpu.dtb.write_hits 41507366 # DTB write hits -system.cpu.dtb.write_misses 32028 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 41539394 # DTB write accesses -system.cpu.dtb.data_hits 167233604 # DTB hits -system.cpu.dtb.data_misses 58730 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 167292334 # DTB accesses -system.cpu.itb.fetch_hits 71588816 # ITB hits +system.cpu.dtb.read_accesses 125958533 # DTB read accesses +system.cpu.dtb.write_hits 41424543 # DTB write hits +system.cpu.dtb.write_misses 32276 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 41456819 # DTB write accesses +system.cpu.dtb.data_hits 167356362 # DTB hits +system.cpu.dtb.data_misses 58990 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 167415352 # DTB accesses +system.cpu.itb.fetch_hits 71387266 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71588856 # ITB accesses +system.cpu.itb.fetch_accesses 71387306 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290351578 # number of cpu cycles simulated +system.cpu.numCycles 290603696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 82068439 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75472139 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4139210 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77758293 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69764860 # Number of BTB hits +system.cpu.BPredUnit.lookups 81919814 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75390266 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4129357 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77614173 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69618230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1965418 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74381248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 740847057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 82068439 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71730278 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139388095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17359106 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 63481916 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1955958 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74192269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 739424750 # Number of instructions fetch has processed +system.cpu.fetch.Branches 81919814 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71574188 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139080989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17172234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64410456 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71588816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1228525 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290282404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.552160 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199400 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 71387266 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1210642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290534603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.545049 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.198246 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150894309 51.98% 51.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11757724 4.05% 56.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15902063 5.48% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15874475 5.47% 66.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13293221 4.58% 71.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15622251 5.38% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6768599 2.33% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3592047 1.24% 80.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56577715 19.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151453614 52.13% 52.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11687885 4.02% 56.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15898742 5.47% 61.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15854935 5.46% 67.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13240035 4.56% 71.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15603650 5.37% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6697784 2.31% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3574182 1.23% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56523776 19.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290282404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.282652 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.551552 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90540829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 49762589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 127167334 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9782311 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13029341 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4494723 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 873 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 729210837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3260 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 13029341 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98854754 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12652695 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 558 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123369042 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42376014 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 715226972 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32893526 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4012041 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 545137745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 939207717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 939205613 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2104 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290534603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281895 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.544444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90310656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 50731551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 126219695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10423604 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12849097 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4446391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 727740839 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3152 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12849097 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98621596 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12675857 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123066068 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43321346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 713725381 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 266 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34127954 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3740820 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 543893835 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 937350842 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 937348775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2067 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 81282856 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 82693608 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131825687 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43890067 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17591169 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7047053 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 644543109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621562613 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 380292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77712656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42125820 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290282404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.141234 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.879500 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 80038946 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 85210895 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131427932 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43788464 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14719547 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6869694 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 643138163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 621184561 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 428348 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 76303449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41228761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 290534603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.138074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876724 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 70571105 24.31% 24.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 58751148 20.24% 44.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 55824387 19.23% 63.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31456534 10.84% 74.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33062190 11.39% 86.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24005083 8.27% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12272709 4.23% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3831324 1.32% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 507924 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 70371393 24.22% 24.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 59001774 20.31% 44.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 56407615 19.42% 63.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31734464 10.92% 74.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32252552 11.10% 85.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24569230 8.46% 94.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11680867 4.02% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3911059 1.35% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 605649 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290282404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290534603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4555010 86.10% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 57 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
