changeset 1f95c9a0bb2f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1f95c9a0bb2f
description:
ARM: Add some MP regressions and clean up the disk images and kernels a
bit
diffstat:
configs/common/Benchmarks.py
| 5 +-
configs/common/FSConfig.py
| 62 +-
tests/SConscript
| 5 +-
tests/configs/realview-o3-dual.py
| 101 +
tests/configs/realview-o3.py
| 4 +-
tests/configs/realview-simple-atomic-dual.py
| 101 +
tests/configs/realview-simple-atomic.py
| 4 +-
tests/configs/realview-simple-timing-dual.py
| 101 +
tests/configs/realview-simple-timing.py
| 4 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
| 1500 ++++++++++
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
| 19 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
| 12 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 1384 +++++++++
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status
| 1 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
| 0
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 72 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
| 2 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1123 +++---
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
| 1 -
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
| 846 +++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
| 18 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
| 12 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 699 ++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
| 1 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 94 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
| 30 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 21 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 768 ++--
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
| 840 +++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
| 18 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
| 12 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 868 +++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
| 1 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 94 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
| 30 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 21 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 938 +++---
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
45 files changed, 8219 insertions(+), 1609 deletions(-)
diffs (truncated from 10654 to 300 lines):
diff -r 6bac5b04d588 -r 1f95c9a0bb2f configs/common/Benchmarks.py
--- a/configs/common/Benchmarks.py Fri Aug 19 15:08:08 2011 -0500
+++ b/configs/common/Benchmarks.py Fri Aug 19 15:08:09 2011 -0500
@@ -56,7 +56,7 @@
elif buildEnv['TARGET_ISA'] == 'x86':
return env.get('LINUX_IMAGE', disk('x86root.img'))
elif buildEnv['TARGET_ISA'] == 'arm':
- return env.get('LINUX_IMAGE', disk('ael-arm.ext2'))
+ return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
else:
print "Don't know what default disk image to use for ISA %s" % \
buildEnv['TARGET_ISA']
@@ -111,9 +111,6 @@
'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
- 'ArmLinux': [SysConfig('null.rcS', '128MB', 'ael-arm.ext2')],
- 'ArmLinuxFrameBuf': [SysConfig('null.rcS', '128MB', 'ael-full.ext2')],
- 'ArmLinuxCflash': [SysConfig('null.rcS', '256MB', 'linux-arm.img')],
'ArmAndroid': [SysConfig('null.rcS', '256MB', 'android-mbr.img')],
}
diff -r 6bac5b04d588 -r 1f95c9a0bb2f configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Fri Aug 19 15:08:08 2011 -0500
+++ b/configs/common/FSConfig.py Fri Aug 19 15:08:09 2011 -0500
@@ -41,6 +41,7 @@
from m5.objects import *
from Benchmarks import *
+from m5.util import convert
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
@@ -216,47 +217,40 @@
print "Unknown Machine Type"
sys.exit(1)
- use_cf = False
- if mdesc.disk()[-4:] == ".img":
- use_cf = True
- self.cf0 = CowIdeDisk(driveID='master')
- self.cf0.childImage(mdesc.disk())
- # default to an IDE controller rather than a CF one
- # assuming we've got one
- try:
- self.realview.ide.disks = [self.cf0]
- except:
- self.realview.cf_ctrl.disks = [self.cf0]
+ self.cf0 = CowIdeDisk(driveID='master')
+ self.cf0.childImage(mdesc.disk())
+ # default to an IDE controller rather than a CF one
+ # assuming we've got one
+ try:
+ self.realview.ide.disks = [self.cf0]
+ except:
+ self.realview.cf_ctrl.disks = [self.cf0]
+
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
zero = True)
else:
- self.kernel = binary('vmlinux.arm')
+ self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
self.machine_type = machine_type
+ if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
+ print "The currently implemented ARM platforms only easily support
256MB of DRAM"
+ print "It might be possible to get some more by using
256MB@0x30000000, but this"
+ print "is untested and may require some heroics"
+
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
- 'rw loglevel=8 '
- if use_cf:
- self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
- zero = True)
- boot_flags += "mem=256MB root=/dev/sda1 "
- self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
- size = '64MB'), zero = True)
- self.nvmem.port = self.membus.port
- self.boot_loader = binary('boot.arm')
- self.boot_loader_mem = self.nvmem
- self.gic_cpu_addr = self.realview.gic.cpu_addr
- self.flags_addr = self.realview.realview_io.pio_addr + 0x30
- else:
- self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')),
- zero = True)
- self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'),
- size = '128MB'),
- file = disk(mdesc.disk()))
- self.diskmem.port = self.membus.port
- boot_flags += "mem=128MB slram=slram0,0x8000000,+0x8000000 " + \
- "mtdparts=slram0:- root=/dev/mtdblock0 "
+ 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
+
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
+ self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
+ size = '64MB'), zero = True)
+ self.nvmem.port = self.membus.port
+ self.boot_loader = binary('boot.arm')
+ self.boot_loader_mem = self.nvmem
+ self.gic_cpu_addr = self.realview.gic.cpu_addr
+ self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if mdesc.disk().count('android'):
boot_flags += "init=/init "
diff -r 6bac5b04d588 -r 1f95c9a0bb2f tests/SConscript
--- a/tests/SConscript Fri Aug 19 15:08:08 2011 -0500
+++ b/tests/SConscript Fri Aug 19 15:08:09 2011 -0500
@@ -277,8 +277,11 @@
't1000-simple-timing']
if env['TARGET_ISA'] == 'arm':
configs += ['realview-simple-atomic',
+ 'realview-simple-atomic-dual',
'realview-simple-timing',
- 'realview-o3']
+ 'realview-simple-timing-dual',
+ 'realview-o3',
+ 'realview-o3-dual']
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
'pc-simple-timing',
diff -r 6bac5b04d588 -r 1f95c9a0bb2f tests/configs/realview-o3-dual.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/realview-o3-dual.py Fri Aug 19 15:08:09 2011 -0500
@@ -0,0 +1,101 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='256MB')
+ forward_snoops = False
+
+#cpu
+cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+system.l2c.num_cpus = 2
+
+#connect up the cpu and l1s
+for c in cpus:
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectAllPorts(system.toL2Bus, system.membus)
+ c.clock = '2GHz'
+
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff -r 6bac5b04d588 -r 1f95c9a0bb2f tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py Fri Aug 19 15:08:08 2011 -0500
+++ b/tests/configs/realview-o3.py Fri Aug 19 15:08:09 2011 -0500
@@ -64,7 +64,7 @@
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
- addr_range=AddrRange(0, size='128MB')
+ addr_range=AddrRange(0, size='256MB')
forward_snoops = False
#cpu
@@ -76,7 +76,7 @@
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
-system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
diff -r 6bac5b04d588 -r 1f95c9a0bb2f
tests/configs/realview-simple-atomic-dual.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/realview-simple-atomic-dual.py Fri Aug 19 15:08:09
2011 -0500
@@ -0,0 +1,101 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
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