changeset 3aaa99208a84 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3aaa99208a84
description:
Ruby: Remove some unused code
diffstat:
src/mem/ruby/buffers/MessageBuffer.cc | 4 ----
src/mem/ruby/common/TypeDefines.hh | 4 ----
src/mem/ruby/network/simple/SimpleNetwork.cc | 13 -------------
src/mem/ruby/system/CacheMemory.hh | 1 -
src/mem/ruby/system/Sequencer.cc | 18 ------------------
src/mem/ruby/system/Sequencer.hh | 3 ---
6 files changed, 0 insertions(+), 43 deletions(-)
diffs (125 lines):
diff -r 00ca5af1b954 -r 3aaa99208a84 src/mem/ruby/buffers/MessageBuffer.cc
--- a/src/mem/ruby/buffers/MessageBuffer.cc Fri Aug 26 12:27:58 2011 -0500
+++ b/src/mem/ruby/buffers/MessageBuffer.cc Mon Aug 29 05:10:23 2011 -0500
@@ -161,16 +161,12 @@
}
m_msgs_this_cycle++;
- // assert(m_max_size == -1 || m_size <= m_max_size + 1);
- // the plus one is a kluge because of a SLICC issue
-
if (!m_ordering_set) {
panic("Ordering property of %s has not been set", m_name);
}
// Calculate the arrival time of the message, that is, the first
// cycle the message can be dequeued.
- //printf ("delta %i \n", delta);
assert(delta>0);
Time current_time = g_eventQueue_ptr->getTime();
Time arrival_time = 0;
diff -r 00ca5af1b954 -r 3aaa99208a84 src/mem/ruby/common/TypeDefines.hh
--- a/src/mem/ruby/common/TypeDefines.hh Fri Aug 26 12:27:58 2011 -0500
+++ b/src/mem/ruby/common/TypeDefines.hh Mon Aug 29 05:10:23 2011 -0500
@@ -40,12 +40,8 @@
typedef long long int64;
typedef long long integer_t;
-typedef unsigned long long uinteger_t;
typedef int64 Time;
typedef uint64 physical_address_t;
-typedef uint64 la_t;
-typedef uint64 pa_t;
-typedef integer_t simtime_t;
#endif
diff -r 00ca5af1b954 -r 3aaa99208a84
src/mem/ruby/network/simple/SimpleNetwork.cc
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc Fri Aug 26 12:27:58
2011 -0500
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc Mon Aug 29 05:10:23
2011 -0500
@@ -30,7 +30,6 @@
#include <numeric>
#include "base/stl_helpers.hh"
-#include "mem/protocol/MachineType.hh"
#include "mem/protocol/TopologyType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/NetDest.hh"
@@ -46,18 +45,6 @@
using namespace std;
using m5::stl_helpers::deletePointers;
-#if 0
-// ***BIG HACK*** - This is actually code that _should_ be in Network.cc
-
-// Note: Moved to Princeton Network
-// calls new to abstract away from the network
-Network*
-Network::createNetwork(int nodes)
-{
- return new SimpleNetwork(nodes);
-}
-#endif
-
SimpleNetwork::SimpleNetwork(const Params *p)
: Network(p)
{
diff -r 00ca5af1b954 -r 3aaa99208a84 src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh Fri Aug 26 12:27:58 2011 -0500
+++ b/src/mem/ruby/system/CacheMemory.hh Mon Aug 29 05:10:23 2011 -0500
@@ -36,7 +36,6 @@
#include "base/hashmap.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/protocol/GenericRequestType.hh"
-#include "mem/protocol/MachineType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
diff -r 00ca5af1b954 -r 3aaa99208a84 src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Fri Aug 26 12:27:58 2011 -0500
+++ b/src/mem/ruby/system/Sequencer.cc Mon Aug 29 05:10:23 2011 -0500
@@ -504,11 +504,6 @@
success ? "Done" : "SC_Failed", "", "",
ruby_request.m_PhysicalAddress, miss_latency);
}
-#if 0
- if (request.getPrefetch() == PrefetchBit_Yes) {
- return; // Ignore the prefetch
- }
-#endif
// update the data
if (ruby_request.data != NULL) {
@@ -702,19 +697,6 @@
m_mandatory_q_ptr->enqueue(msg, latency);
}
-#if 0
-bool
-Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
- RubyAccessMode access_mode,
- int size, DataBlock*& data_ptr)
-{
- CacheMemory *cache =
- (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
-
- return cache->tryCacheAccess(line_address(addr), type, data_ptr);
-}
-#endif
-
template <class KEY, class VALUE>
std::ostream &
operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
diff -r 00ca5af1b954 -r 3aaa99208a84 src/mem/ruby/system/Sequencer.hh
--- a/src/mem/ruby/system/Sequencer.hh Fri Aug 26 12:27:58 2011 -0500
+++ b/src/mem/ruby/system/Sequencer.hh Mon Aug 29 05:10:23 2011 -0500
@@ -112,9 +112,6 @@
void removeRequest(SequencerRequest* request);
private:
- bool tryCacheAccess(const Address& addr, RubyRequestType type,
- const Address& pc, RubyAccessMode access_mode,
- int size, DataBlock*& data_ptr);
void issueRequest(const RubyRequest& request);
void hitCallback(SequencerRequest* request,
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