Do the cache models in M5 support Cache Injection? I've created a simulation where I have a memory mapped NIC that uses a DmaDevice to read and write physical memory (note the memory is not restricted to UNCACHEABLE). I've followed WriteReq packets from the DmaDevice to the Cache and it appears that the data in these packets is not injected into the cache even if the cache block is present. I've hacked handleSnoop() so it injects write request into the cache if the cache block is present. This hack has allowed me to run MPI apps such as osu_bw and osu_latency but I'm running into a problem, with another app, that looks like a memory consistency issue. I'd consider my use of the DmaDevice to be pretty standard so I'm stumped why I'm having a problem unless using it to access CACHEABLE memory is not allowed.
Note that I'm using a snapshot of M5 from last fall. Michael Levenhagen Sandia National Labs. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
