changeset d04ae08781e2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d04ae08781e2
description:
X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a
translation
could be completed immediately, or if there's going to be callback that
will
finish things up. If a read was to the internal memory space, memory
mapped
registers used to implement things like MSRs, the function hadn't yet
gotten
to where delayedResponse was set to false, it's default. That meant
that the
value was never set, and the TLB could start waiting for a callback
that would
never come. This change simply moves the assignment to above where
control
can divert to translateInt().
diffstat:
src/arch/x86/tlb.cc | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (19 lines):
diff -r 09745e0c3dd9 -r d04ae08781e2 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Sep 02 17:04:00 2011 -0700
+++ b/src/arch/x86/tlb.cc Mon Sep 05 02:48:57 2011 -0700
@@ -539,13 +539,14 @@
int seg = flags & SegmentFlagMask;
bool storeCheck = flags & (StoreCheck << FlagShift);
+ delayedResponse = false;
+
// If this is true, we're dealing with a request to a non-memory address
// space.
if (seg == SEGMENT_REG_MS) {
return translateInt(req, tc);
}
- delayedResponse = false;
Addr vaddr = req->getVaddr();
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
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