changeset 66b311535265 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=66b311535265 description: MIPS: Update MIPS stats for cleaned up operand checks.
diffstat: tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini | 3 +- tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 6 +- tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 14 +- tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini | 1 + tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr | 1 - tests/quick/00.hello/ref/mips/linux/simple-atomic/simout | 16 +- tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt | 70 +- tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini | 121 +- tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr | 1 - tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout | 16 +- tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | 70 +- tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 1 + tests/quick/00.hello/ref/mips/linux/simple-timing/simerr | 1 - tests/quick/00.hello/ref/mips/linux/simple-timing/simout | 16 +- tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt | 422 +++++----- 15 files changed, 384 insertions(+), 375 deletions(-) diffs (truncated from 1047 to 300 lines): diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini Fri Sep 09 01:35:05 2011 -0700 @@ -102,6 +102,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/o3-timing/simout --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout Fri Sep 09 01:35:05 2011 -0700 @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:48:05 -gem5 started Jul 15 2011 20:13:48 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Sep 9 2011 01:24:08 +gem5 started Sep 9 2011 01:24:15 +gem5 executing on chips command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt Fri Sep 09 01:35:05 2011 -0700 @@ -3,10 +3,10 @@ sim_seconds 0.000012 # Number of seconds simulated sim_ticks 12273500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33014 # Simulator instruction rate (inst/s) -host_tick_rate 78373339 # Simulator tick rate (ticks/s) -host_mem_usage 244788 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 39169 # Simulator instruction rate (inst/s) +host_tick_rate 92983194 # Simulator tick rate (ticks/s) +host_mem_usage 242872 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -86,9 +86,9 @@ system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13125 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 13124 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups +system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18 # count of serializing insts renamed @@ -290,7 +290,7 @@ system.cpu.int_regfile_writes 4991 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 154 # number of misc regfile reads +system.cpu.misc_regfile_reads 153 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use system.cpu.icache.total_refs 1364 # Total number of references to valid blocks. diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini Fri Sep 09 01:35:05 2011 -0700 @@ -9,6 +9,7 @@ type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr Fri Sep 09 01:35:05 2011 -0700 @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/simple-atomic/simout --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout Fri Sep 09 01:35:05 2011 -0700 @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:18:54 -M5 started Apr 19 2011 12:18:58 -M5 executing on maize -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic +gem5 compiled Sep 9 2011 01:24:08 +gem5 started Sep 9 2011 01:24:15 +gem5 executing on chips +command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt Fri Sep 09 01:35:05 2011 -0700 @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 798153 # Simulator instruction rate (inst/s) -host_mem_usage 195780 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 390049435 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5827 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated sim_ticks 2913500 # Number of ticks simulated -system.cpu.dtb.accesses 0 # DTB accesses +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 550881 # Simulator instruction rate (inst/s) +host_tick_rate 274282730 # Simulator tick rate (ticks/s) +host_mem_usage 232848 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 5827 # Number of instructions simulated +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 0 # DTB accesses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 8 # Number of system calls system.cpu.numCycles 5828 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 5828 # Number of busy cycles +system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_func_calls 194 # number of times a function call or return occured system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_int_insts 5126 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_int_register_reads 7300 # number of times the integer registers were read +system.cpu.num_int_register_writes 3409 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_func_calls 194 # number of times a function call or return occured +system.cpu.num_mem_refs 2090 # number of memory refs +system.cpu.num_load_insts 1164 # Number of load instructions +system.cpu.num_store_insts 926 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses -system.cpu.num_int_insts 5126 # number of integer instructions -system.cpu.num_int_register_reads 7301 # number of times the integer registers were read -system.cpu.num_int_register_writes 3409 # number of times the integer registers were written -system.cpu.num_load_insts 1164 # Number of load instructions -system.cpu.num_mem_refs 2090 # number of memory refs -system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.workload.num_syscalls 8 # Number of system calls +system.cpu.num_busy_cycles 5828 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff -r 7d3ea3c65c66 -r 66b311535265 tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini Fri Sep 09 01:01:43 2011 -0700 +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini Fri Sep 09 01:35:05 2011 -0700 @@ -9,6 +9,7 @@ type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -41,8 +42,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.cpu_ruby_ports.port[1] -icache_port=system.ruby.cpu_ruby_ports.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=MipsTLB @@ -78,11 +79,13 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 +cntrl_id=1 directory=system.dir_cntrl0.directory directory_latency=12 memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -117,16 +120,42 @@ [system.l1_cntrl0] type=L1Cache_Controller +children=cacheMemory sequencer buffer_size=0 -cacheMemory=system.ruby.cpu_ruby_ports.dcache +cacheMemory=system.l1_cntrl0.cacheMemory cache_response_latency=12 +cntrl_id=0 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + [system.physmem] type=PhysicalMemory file= @@ -135,44 +164,18 @@ null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler tracer _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
