changeset 7cff2156c998 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7cff2156c998
description:
ARM: Implement numcpus bits in L2CTLR register.
diffstat:
src/arch/arm/isa.cc | 9 +++++++++
src/arch/arm/miscregs.cc | 14 +++++++++++++-
src/arch/arm/miscregs.hh | 19 +++++++++++++++++++
3 files changed, 41 insertions(+), 1 deletions(-)
diffs (93 lines):
diff -r 33bdc36bf46f -r 7cff2156c998 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/isa.cc Tue Sep 13 12:06:13 2011 -0500
@@ -227,6 +227,12 @@
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
case MISCREG_FPSCR_EXC:
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
+ case MISCREG_L2CTLR:
+ // mostly unimplemented, just set NumCPUs field from sim and return
+ L2CTLR l2ctlr = 0;
+ // b00:1CPU to b11:4CPUs
+ l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
+ return l2ctlr;
}
return readMiscRegNoEffect(misc_reg);
}
@@ -537,6 +543,9 @@
// see all of the registers for the copy.
updateRegMap(val);
return;
+ case MISCREG_L2CTLR:
+ warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
+ miscRegName[misc_reg], uint32_t(val));
}
}
setMiscRegNoEffect(misc_reg, newVal);
diff -r 33bdc36bf46f -r 7cff2156c998 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/miscregs.cc Tue Sep 13 12:06:13 2011 -0500
@@ -382,7 +382,19 @@
}
}
} else if (opc1 == 1) {
- return MISCREG_L2LATENCY;
+ switch (crm) {
+ case 0:
+ switch (opc2) {
+ case 2: // L2CTLR, L2 Control Register
+ return MISCREG_L2CTLR;
+ default:
+ warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
+ crn,crm, opc1,opc2);
+ break;
+ }
+ default:
+ return MISCREG_L2LATENCY;
+ }
}
//Reserved for Branch Predictor, Cache and TCM operations
break;
diff -r 33bdc36bf46f -r 7cff2156c998 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/miscregs.hh Tue Sep 13 12:06:13 2011 -0500
@@ -177,6 +177,7 @@
MISCREG_LOCKFLAG,
MISCREG_LOCKADDR,
MISCREG_ID_PFR1,
+ MISCREG_L2CTLR,
MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_DFR0,
@@ -238,6 +239,7 @@
"pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
+ "l2ctlr",
// Unimplemented below
"tcmtr",
"id_dfr0", "id_afr0",
@@ -432,6 +434,23 @@
Bitfield<31,30> or7;
EndBitUnion(NMRR)
+ BitUnion32(L2CTLR)
+ Bitfield<2,0> sataRAMLatency;
+ Bitfield<4,3> reserved_4_3;
+ Bitfield<5> dataRAMSetup;
+ Bitfield<8,6> tagRAMLatency;
+ Bitfield<9> tagRAMSetup;
+ Bitfield<11,10> dataRAMSlice;
+ Bitfield<12> tagRAMSlice;
+ Bitfield<20,13> reserved_20_13;
+ Bitfield<21> eccandParityEnable;
+ Bitfield<22> reserved_22;
+ Bitfield<23> interptCtrlPresent;
+ Bitfield<25,24> numCPUs;
+ Bitfield<30,26> reserved_30_26;
+ Bitfield<31> l2rstDISABLE_monitor;
+ EndBitUnion(L2CTLR)
+
};
#endif // __ARCH_ARM_MISCREGS_HH__
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