changeset 8ac6c1fa657f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8ac6c1fa657f
description:
CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not
implemented.
diffstat:
src/arch/arm/isa/formats/misc.isa | 3 +++
src/arch/arm/miscregs.cc | 2 +-
src/arch/arm/miscregs.hh | 2 ++
3 files changed, 6 insertions(+), 1 deletions(-)
diffs (44 lines):
diff -r 7cff2156c998 -r 8ac6c1fa657f src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/isa/formats/misc.isa Tue Sep 13 12:06:13 2011 -0500
@@ -143,6 +143,9 @@
case MISCREG_L2LATENCY:
return new WarnUnimplemented(
isRead ? "mrc l2latency" : "mcr l2latency", machInst);
+ case MISCREG_CRN15:
+ return new WarnUnimplemented(
+ isRead ? "mrc crn15" : "mcr crn15", machInst);
// Write only.
case MISCREG_TLBIALLIS:
diff -r 7cff2156c998 -r 8ac6c1fa657f src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/miscregs.cc Tue Sep 13 12:06:13 2011 -0500
@@ -463,7 +463,7 @@
break;
case 15:
// Implementation defined
- break;
+ return MISCREG_CRN15;
}
// Unrecognized register
return NUM_MISCREGS;
diff -r 7cff2156c998 -r 8ac6c1fa657f src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/miscregs.hh Tue Sep 13 12:06:13 2011 -0500
@@ -196,6 +196,7 @@
MISCREG_ISR,
MISCREG_FCEIDR,
MISCREG_L2LATENCY,
+ MISCREG_CRN15,
MISCREG_CP15_END,
@@ -249,6 +250,7 @@
"dccmvau",
"nsacr",
"vbar", "mvbar", "isr", "fceidr", "l2latency",
+ "crn15",
"nop", "raz"
};
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