changeset f81bcb16fa1b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f81bcb16fa1b
description:
MIPS: Get rid of #if style config checks in the ISA description.
diffstat:
src/arch/mips/isa/decoder.isa | 90 +++++++-----------------
src/arch/mips/isa/formats/control.isa | 124 ++++++++++++++-------------------
src/arch/mips/isa/formats/dsp.isa | 22 +----
src/arch/mips/isa/formats/fp.isa | 17 ++--
src/arch/mips/isa/formats/mem.isa | 16 ++--
src/arch/mips/isa/formats/unimp.isa | 67 +++++++++---------
src/arch/mips/isa/includes.isa | 3 +
7 files changed, 137 insertions(+), 202 deletions(-)
diffs (truncated from 505 to 300 lines):
diff -r 58cf8f4a7c33 -r f81bcb16fa1b src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Mon Sep 19 06:09:15 2011 -0700
+++ b/src/arch/mips/isa/decoder.isa Mon Sep 19 06:14:02 2011 -0700
@@ -163,12 +163,11 @@
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
-#if FULL_SYSTEM
- 0x4: syscall({{ fault = new SystemCallFault(); }});
-#else
- 0x4: syscall({{ xc->syscall(R2); }},
- IsSerializeAfter, IsNonSpeculative);
-#endif
+ 0x4: decode FULL_SYSTEM {
+ 0: syscall_se({{ xc->syscall(R2); }},
+ IsSerializeAfter, IsNonSpeculative);
+ default: syscall({{ fault = new SystemCallFault(); }});
+ }
0x7: sync({{ ; }}, IsMemBarrier);
0x5: break({{fault = new BreakpointFault();}});
}
@@ -211,44 +210,21 @@
0x0: decode FUNCTION_LO {
format IntOp {
0x0: add({{
- /* More complicated since an ADD can cause
- an arithmetic overflow exception */
- int64_t Src1 = Rs.sw;
- int64_t Src2 = Rt.sw;
- int64_t temp_result;
-#if FULL_SYSTEM
- if (((Src1 >> 31) & 1) == 1)
- Src1 |= 0x100000000LL;
-#endif
- temp_result = Src1 + Src2;
-#if FULL_SYSTEM
- if (bits(temp_result, 31) ==
- bits(temp_result, 32)) {
-#endif
- Rd.sw = temp_result;
-#if FULL_SYSTEM
- } else {
+ IntReg result;
+ Rd = result = Rs + Rt;
+ if (FULL_SYSTEM &&
+ findOverflow(32, result, Rs, Rt)) {
fault = new ArithmeticFault();
}
-#endif
}});
0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
0x2: sub({{
- /* More complicated since an SUB can cause
- an arithmetic overflow exception */
- int64_t Src1 = Rs.sw;
- int64_t Src2 = Rt.sw;
- int64_t temp_result = Src1 - Src2;
-#if FULL_SYSTEM
- if (bits(temp_result, 31) ==
- bits(temp_result, 32)) {
-#endif
- Rd.sw = temp_result;
-#if FULL_SYSTEM
- } else {
+ IntReg result;
+ Rd = result = Rs - Rt;
+ if (FULL_SYSTEM &&
+ findOverflow(32, result, Rs, ~Rt)) {
fault = new ArithmeticFault();
}
-#endif
}});
0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }});
0x4: and({{ Rd = Rs & Rt; }});
@@ -347,23 +323,12 @@
0x1: decode OPCODE_LO {
format IntImmOp {
0x0: addi({{
- int64_t Src1 = Rs.sw;
- int64_t Src2 = imm;
- int64_t temp_result;
-#if FULL_SYSTEM
- if (((Src1 >> 31) & 1) == 1)
- Src1 |= 0x100000000LL;
-#endif
- temp_result = Src1 + Src2;
-#if FULL_SYSTEM
- if (bits(temp_result, 31) == bits(temp_result, 32)) {
-#endif
- Rt.sw = temp_result;
-#if FULL_SYSTEM
- } else {
+ IntReg result;
+ Rt = result = Rs + imm;
+ if (FULL_SYSTEM &&
+ findOverflow(32, result, Rs, imm)) {
fault = new ArithmeticFault();
}
-#endif
}});
0x1: addiu({{ Rt.sw = Rs.sw + imm; }});
0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }});
@@ -1516,11 +1481,10 @@
if (Rs<2:0> == 0) {
Fd.ud = Fs.ud;
} else if (Rs<2:0> == 4) {
-#if BYTE_ORDER == BIG_ENDIAN
- Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;
-#elif BYTE_ORDER == LITTLE_ENDIAN
- Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>;
-#endif
+ if (GuestByteOrder == BigEndianByteOrder)
+ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;
+ else
+ Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>;
} else {
Fd.ud = Fd.ud;
}
@@ -2468,14 +2432,12 @@
}
}
}
- 0x3: decode OP {
-#if FULL_SYSTEM
- 0x0: FailUnimpl::rdhwr();
-#else
- 0x0: decode RD {
- 29: BasicOp::rdhwr({{ Rt = TpValue; }});
+ 0x3: decode OP default FailUnimpl::rdhwr() {
+ 0x0: decode FULL_SYSTEM {
+ 0: decode RD {
+ 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
+ }
}
-#endif
}
}
}
diff -r 58cf8f4a7c33 -r f81bcb16fa1b src/arch/mips/isa/formats/control.isa
--- a/src/arch/mips/isa/formats/control.isa Mon Sep 19 06:09:15 2011 -0700
+++ b/src/arch/mips/isa/formats/control.isa Mon Sep 19 06:14:02 2011 -0700
@@ -124,30 +124,28 @@
def template ControlTLBExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
- %(op_decl)s;
- %(op_rd)s;
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
-#if FULL_SYSTEM
+ if (FULL_SYSTEM) {
if (isCoprocessor0Enabled(xc)) {
- if(isMMUTLB(xc)){
- %(code)s;
- } else {
- fault = new ReservedInstructionFault();
- }
+ if(isMMUTLB(xc)){
+ %(code)s;
+ } else {
+ fault = new ReservedInstructionFault();
+ }
} else {
- fault = new CoprocessorUnusableFault(0);
+ fault = new CoprocessorUnusableFault(0);
}
-#else // Syscall Emulation Mode - No TLB Instructions
+ } else { // Syscall Emulation Mode - No TLB Instructions
fault = new ReservedInstructionFault();
-#endif
+ }
- if(fault == NoFault)
- {
- %(op_wb)s;
- }
- return fault;
-
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
}
}};
@@ -175,67 +173,49 @@
}};
output exec {{
- bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
+ bool
+ isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
-#if !FULL_SYSTEM
- return true;
-#else
- MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
- switch(cop_num)
- {
- case 0:
- {
- MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
- if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0
accessible
- && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
- && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode
is base mode
- // Unable to use Status_CU0, etc directly, using
bitfields & masks
- return false;
- }
+ if (!FULL_SYSTEM)
+ return true;
- }
- break;
- case 1:
- if((Stat & 0x20000000) == 0) // CU1 is reset
- return false;
- break;
- case 2:
- if((Stat & 0x40000000) == 0) // CU2 is reset
- return false;
- break;
- case 3:
- if((Stat & 0x80000000) == 0) // CU3 is reset
- return false;
- break;
- default: panic("Invalid Coprocessor Number Specified");
- break;
+ MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
+ if (cop_num == 0) {
+ MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
+ // In Stat, EXL, ERL or CU0 set, CP0 accessible
+ // In Dbg, DM bit set, CP0 accessible
+ // In Stat, KSU = 0, kernel mode is base mode
+ return (Stat & 0x10000006) ||
+ (Dbg & 0x40000000) ||
+ !(Stat & 0x00000018);
+ } else if (cop_num < 4) {
+ return Stat & (0x10000000 << cop_num); // CU is reset
+ } else {
+ panic("Invalid Coprocessor Number Specified");
}
- return true;
-#endif
}
- bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
+
+ bool inline
+ isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
-#if FULL_SYSTEM
- MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS);
- MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG);
- if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
- && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
- && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is
base mode
- // Unable to use Status_CU0, etc directly, using bitfields &
masks
- return false;
- }
-#else
- //printf("Syscall Emulation Mode: CP0 Enable Check defaults to
TRUE\n");
-#endif
- return true;
+ if (FULL_SYSTEM) {
+ MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
+ MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
+ // In Stat, EXL, ERL or CU0 set, CP0 accessible
+ // In Dbg, DM bit set, CP0 accessible
+ // In Stat KSU = 0, kernel mode is base mode
+ return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
+ !(Stat & 0x00000018);
+ } else {
+ return true;
+ }
}
- bool isMMUTLB(%(CPU_exec_context)s *xc)
+
+ bool
+ isMMUTLB(%(CPU_exec_context)s *xc)
{
-#if FULL_SYSTEM
- if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80)
- return true;
-#endif
- return false;
+ MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
+ return FULL_SYSTEM && (Config & 0x380) == 0x80;
}
}};
diff -r 58cf8f4a7c33 -r f81bcb16fa1b src/arch/mips/isa/formats/dsp.isa
--- a/src/arch/mips/isa/formats/dsp.isa Mon Sep 19 06:09:15 2011 -0700
+++ b/src/arch/mips/isa/formats/dsp.isa Mon Sep 19 06:14:02 2011 -0700
@@ -140,28 +140,18 @@
}};
output exec {{
- bool isDspEnabled(%(CPU_exec_context)s *xc)
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