changeset be51bef13962 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=be51bef13962
description:
MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of
having two
different classes. The classes were also misleadingly named since loads
are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I
haven't
looked at it closely.
diffstat:
src/arch/mips/faults.cc | 84 +++++-------------------------------------------
src/arch/mips/faults.hh | 48 +++++----------------------
src/arch/mips/tlb.cc | 8 ++--
3 files changed, 23 insertions(+), 117 deletions(-)
diffs (242 lines):
diff -r 62d4b366546f -r be51bef13962 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Mon Sep 19 06:17:20 2011 -0700
+++ b/src/arch/mips/faults.cc Mon Sep 19 06:17:20 2011 -0700
@@ -85,17 +85,11 @@
template <> FaultVals MipsFault<BreakpointFault>::vals =
{ "Breakpoint", 0x0180 };
-template <> FaultVals MipsFault<ItbInvalidFault>::vals =
- { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
+template <> FaultVals MipsFault<TlbInvalidFault>::vals =
+ { "Invalid TLB Entry Exception", 0x0180 };
-template <> FaultVals MipsFault<ItbRefillFault>::vals =
- { "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
-
-template <> FaultVals MipsFault<DtbInvalidFault>::vals =
- { "Invalid TLB Entry Exception (Store)", 0x0180 };
-
-template <> FaultVals MipsFault<DtbRefillFault>::vals =
- { "TLB Refill Exception (Store)", 0x0180 };
+template <> FaultVals MipsFault<TlbRefillFault>::vals =
+ { "TLB Refill Exception", 0x0180 };
template <> FaultVals MipsFault<TLBModifiedFault>::vals =
{ "TLB Modified Exception", 0x0180 };
@@ -199,9 +193,10 @@
}
void
-DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
+ setExceptionState(tc, store ? 0x3 : 0x2);
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
@@ -213,8 +208,6 @@
ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
context.badVPN2 = contextBadVPN2;
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
- setExceptionState(tc, 0x3);
-
// Set new PC
Addr HandlerBase;
@@ -238,35 +231,11 @@
}
void
-ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0x2);
- tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
- entryHi.asid = entryHiAsid;
- entryHi.vpn2 = entryHiVPN2;
- entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
-
- ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
- context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
-
-
- // Set new PC
- Addr HandlerBase;
- // Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
- setHandlerPC(HandlerBase,tc);
- DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
- HandlerBase, tc->readMiscReg(MISCREG_EPC));
-}
-
-void
-ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
+ setExceptionState(tc, store ? 0x3 : 0x2);
+
Addr HandlerBase;
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
@@ -288,41 +257,6 @@
// Offset 0x000
HandlerBase = tc->readMiscReg(MISCREG_EBASE);
}
-
- setExceptionState(tc, 0x2);
- setHandlerPC(HandlerBase, tc);
-}
-
-void
-DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- // Set new PC
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- Addr HandlerBase;
- tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
- entryHi.asid = entryHiAsid;
- entryHi.vpn2 = entryHiVPN2;
- entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
-
- ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
- context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
-
- StatusReg status = tc->readMiscReg(MISCREG_STATUS);
- // Since handler depends on EXL bit, must check EXL bit before setting it!!
- // See MIPS ARM Vol 3, Revision 2, Page 38
- if (status.exl) {
- // Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
- } else {
- // Offset 0x000
- HandlerBase = tc->readMiscReg(MISCREG_EBASE);
- }
-
- setExceptionState(tc, 0x3);
-
setHandlerPC(HandlerBase, tc);
}
diff -r 62d4b366546f -r be51bef13962 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh Mon Sep 19 06:17:20 2011 -0700
+++ b/src/arch/mips/faults.hh Mon Sep 19 06:17:20 2011 -0700
@@ -199,10 +199,13 @@
#endif
};
-class ItbRefillFault : public MipsFault<ItbRefillFault>
+class TlbRefillFault : public MipsFault<TlbRefillFault>
{
+ protected:
+ bool store;
public:
- ItbRefillFault(Addr asid, Addr vaddr, Addr vpn)
+ TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool _store) :
+ store(_store)
{
entryHiAsid = asid;
entryHiVPN2 = vpn >> 2;
@@ -216,27 +219,13 @@
#endif
};
-class DtbRefillFault : public MipsFault<DtbRefillFault>
+class TlbInvalidFault : public MipsFault<TlbInvalidFault>
{
+ protected:
+ bool store;
public:
- DtbRefillFault(Addr asid, Addr vaddr, Addr vpn)
- {
- entryHiAsid = asid;
- entryHiVPN2 = vpn >> 2;
- entryHiVPN2X = vpn & 0x3;
- badVAddr = vaddr;
- contextBadVPN2 = vpn >> 2;
- }
-#if FULL_SYSTEM
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
-};
-
-class ItbInvalidFault : public MipsFault<ItbInvalidFault>
-{
- public:
- ItbInvalidFault(Addr asid, Addr vaddr, Addr vpn)
+ TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool _store) :
+ store(_store)
{
entryHiAsid = asid;
entryHiVPN2 = vpn >> 2;
@@ -267,23 +256,6 @@
#endif
};
-class DtbInvalidFault : public MipsFault<DtbInvalidFault>
-{
- public:
- DtbInvalidFault(Addr asid, Addr vaddr, Addr vpn)
- {
- entryHiAsid = asid;
- entryHiVPN2 = vpn >> 2;
- entryHiVPN2X = vpn & 0x3;
- badVAddr = vaddr;
- contextBadVPN2 = vpn >> 2;
- }
-#if FULL_SYSTEM
- void invoke(ThreadContext * tc,
- StaticInst::StaticInstPtr inst = nullStaticInstPtr);
-#endif
-};
-
class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
{
public:
diff -r 62d4b366546f -r be51bef13962 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Mon Sep 19 06:17:20 2011 -0700
+++ b/src/arch/mips/tlb.cc Mon Sep 19 06:17:20 2011 -0700
@@ -352,7 +352,7 @@
}
if (Valid == false) {
- return new ItbInvalidFault(Asid, vaddr, vpn);
+ return new InvalidFault(Asid, vaddr, vpn, false);
} else {
// Ok, this is really a match, set paddr
Addr PAddr;
@@ -368,7 +368,7 @@
}
} else {
// Didn't find any match, return a TLB Refill Exception
- return new ItbRefillFault(Asid, vaddr, vpn);
+ return new RefillFault(Asid, vaddr, vpn, false);
}
}
return checkCacheability(req);
@@ -447,7 +447,7 @@
}
if (Valid == false) {
- return new DtbInvalidFault(Asid, vaddr, VPN);
+ return new InvalidFault(Asid, vaddr, VPN, true);
} else {
// Ok, this is really a match, set paddr
if (!Dirty) {
@@ -466,7 +466,7 @@
}
} else {
// Didn't find any match, return a TLB Refill Exception
- return new DtbRefillFault(Asid, vaddr, VPN);
+ return new RefillFault(Asid, vaddr, VPN, true);
}
}
return checkCacheability(req);
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