changeset dee1f3ab92e4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dee1f3ab92e4
description:
MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that
gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and
adds
names for the exception code constants.
diffstat:
src/arch/mips/faults.cc | 231 ++++++++--------------------------
src/arch/mips/faults.hh | 312 ++++++++++++++++++++++++++---------------------
2 files changed, 228 insertions(+), 315 deletions(-)
diffs (truncated from 663 to 300 lines):
diff -r 37dbd858c367 -r dee1f3ab92e4 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Mon Sep 19 06:17:21 2011 -0700
+++ b/src/arch/mips/faults.cc Mon Sep 19 06:17:21 2011 -0700
@@ -48,54 +48,56 @@
typedef MipsFaultBase::FaultVals FaultVals;
+template <> FaultVals MipsFault<SystemCallFault>::vals =
+ { "Syscall", 0x180, ExcCodeSys };
+
+template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
+ { "Reserved Instruction Fault", 0x180, ExcCodeRI };
+
+template <> FaultVals MipsFault<ThreadFault>::vals =
+ { "Thread Fault", 0x180, ExcCodeDummy };
+
+template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
+ { "Integer Overflow Exception", 0x180, ExcCodeOv };
+
+template <> FaultVals MipsFault<TrapFault>::vals =
+ { "Trap", 0x180, ExcCodeTr };
+
+template <> FaultVals MipsFault<BreakpointFault>::vals =
+ { "Breakpoint", 0x180, ExcCodeBp };
+
+template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
+ { "DSP Disabled Fault", 0x180, ExcCodeDummy };
+
template <> FaultVals MipsFault<MachineCheckFault>::vals =
- { "Machine Check", 0x0401 };
+ { "Machine Check", 0x180, ExcCodeMCheck };
template <> FaultVals MipsFault<ResetFault>::vals =
-#if FULL_SYSTEM
- { "Reset Fault", 0xBFC00000};
-#else
- { "Reset Fault", 0x001};
-#endif
+ { "Reset Fault", 0x000, ExcCodeDummy };
+
+template <> FaultVals MipsFault<SoftResetFault>::vals =
+ { "Soft Reset Fault", 0x000, ExcCodeDummy };
+
+template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
+ { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
+
+template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
+ { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
+
+template <> FaultVals MipsFault<InterruptFault>::vals =
+ { "Interrupt", 0x000, ExcCodeInt };
template <> FaultVals MipsFault<AddressErrorFault>::vals =
- { "Address Error", 0x0180 };
-
-template <> FaultVals MipsFault<SystemCallFault>::vals =
- { "Syscall", 0x0180 };
-
-template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
- { "Coprocessor Unusable Fault", 0x180 };
-
-template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
- { "Reserved Instruction Fault", 0x0180 };
-
-template <> FaultVals MipsFault<ThreadFault>::vals =
- { "Thread Fault", 0x00F1 };
-
-template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
- { "Integer Overflow Exception", 0x180 };
-
-template <> FaultVals MipsFault<InterruptFault>::vals =
- { "interrupt", 0x0180 };
-
-template <> FaultVals MipsFault<TrapFault>::vals =
- { "Trap", 0x0180 };
-
-template <> FaultVals MipsFault<BreakpointFault>::vals =
- { "Breakpoint", 0x0180 };
+ { "Address Error", 0x180, ExcCodeDummy };
template <> FaultVals MipsFault<TlbInvalidFault>::vals =
- { "Invalid TLB Entry Exception", 0x0180 };
+ { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
template <> FaultVals MipsFault<TlbRefillFault>::vals =
- { "TLB Refill Exception", 0x0180 };
+ { "TLB Refill Exception", 0x180, ExcCodeDummy };
template <> FaultVals MipsFault<TlbModifiedFault>::vals =
- { "TLB Modified Exception", 0x0180 };
-
-template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
- { "DSP Disabled Fault", 0x001a };
+ { "TLB Modified Exception", 0x180, ExcCodeMod };
void
MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
@@ -129,118 +131,28 @@
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
}
-#if FULL_SYSTEM
-
void
-IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0xC);
-
- // Set new PC
- StatusReg status = tc->readMiscReg(MISCREG_STATUS);
- if (!status.bev) {
- // See MIPS ARM Vol 3, Revision 2, Page 38
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
+ if (FULL_SYSTEM) {
+ DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
+ setExceptionState(tc, code());
+ tc->pcState(vect(tc));
} else {
- tc->pcState(0xBFC00200);
+ panic("Fault %s encountered.\n", name());
}
}
void
-TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0xD);
-
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-}
-
-void
-BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- setExceptionState(tc, 0x9);
-
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-}
-
-void
-AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, store ? 0x5 : 0x4);
- tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
-
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-}
-
-void
-TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- setTlbExceptionState(tc, store ? 0x3 : 0x2);
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-}
-
-void
-TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- // Since handler depends on EXL bit, must check EXL bit before setting it!!
- StatusReg status = tc->readMiscReg(MISCREG_STATUS);
-
- setTlbExceptionState(tc, store ? 0x3 : 0x2);
-
- // See MIPS ARM Vol 3, Revision 2, Page 38
- if (status.exl == 1) {
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
- } else {
- tc->pcState(tc->readMiscReg(MISCREG_EBASE));
- }
-}
-
-void
-TlbModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- setTlbExceptionState(tc, 0x1);
-
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-}
-
-void
-SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0x8);
-
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-}
-
-void
-InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0x0A);
-
- CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
- if (cause.iv) {
- // Offset 200 for release 2
- tc->pcState(0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
- } else {
- //Ofset at 180 for release 1
- tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
- }
-}
-
-#endif // FULL_SYSTEM
-
-void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
-#if FULL_SYSTEM
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- /* All reset activity must be invoked from here */
- tc->pcState(vect());
- DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
-#endif
+ if (FULL_SYSTEM) {
+ DPRINTF(MipsPRA, "%s encountered.\n", name());
+ /* All reset activity must be invoked from here */
+ Addr handler = vect(tc);
+ tc->pcState(handler);
+ DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
+ }
// Set Coprocessor 1 (Floating Point) To Usable
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
@@ -249,46 +161,15 @@
}
void
-ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
-#if FULL_SYSTEM
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0x0A);
- tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
-#else
- panic("%s encountered.\n", name());
-#endif
+ panic("Soft reset not implemented.\n");
}
void
-ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- panic("%s encountered.\n", name());
-}
-
-void
-DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- panic("%s encountered.\n", name());
-}
-
-void
-CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
-#if FULL_SYSTEM
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0xb);
- // The ID of the coprocessor causing the exception is stored in
- // CoprocessorUnusableFault::coProcID
- CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
- cause.ce = coProcID;
- tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
- tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
-#else
- warn("%s (CP%d) encountered.\n", name(), coProcID);
-#endif
+ panic("Non maskable interrupt not implemented.\n");
}
} // namespace MipsISA
diff -r 37dbd858c367 -r dee1f3ab92e4 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh Mon Sep 19 06:17:21 2011 -0700
+++ b/src/arch/mips/faults.hh Mon Sep 19 06:17:21 2011 -0700
@@ -44,21 +44,63 @@
typedef const Addr FaultVect;
+enum ExcCode {
+ // A dummy value to use when the code isn't defined or doesn't matter.
+ ExcCodeDummy = 0,
+
+ ExcCodeInt = 0,
+ ExcCodeMod = 1,
+ ExcCodeTlbL = 2,
+ ExcCodeTlbS = 3,
+ ExcCodeAdEL = 4,
+ ExcCodeAdES = 5,
+ ExcCodeIBE = 6,
+ ExcCodeDBE = 7,
+ ExcCodeSys = 8,
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