changeset ef28ed90449d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ef28ed90449d
description:
ISA parser: Use '_' instead of '.' to delimit type modifiers on
operands.
By using an underscore, the "." is still available and can
unambiguously be
used to refer to members of a structure if an operand is a structure,
class,
etc. This change mostly just replaces the appropriate "."s with "_"s,
but
there were also a few places where the ISA descriptions where handling
the
extensions themselves and had their own regular expressions to update.
The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after
connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This
helps to
disambiguate cases where a "_" may legitimately be part of an operand
name but
not separate the name from the type suffix.
Because leaving the "_" and suffix on the variable name still leaves a
valid
C++ identifier and all extensions need to be consistent in a given
context, I
considered leaving them on as a breadcrumb that would show what the
intended
type was for that operand. Unfortunately the operands can be referred
to in
code templates, the Mem operand in particular, and since the exact type
of Mem
can be different for different uses of the same template, that broke
things.
diffstat:
src/arch/alpha/isa/decoder.isa | 264 +++++-----
src/arch/alpha/isa/int.isa | 2 +-
src/arch/alpha/isa/main.isa | 2 +-
src/arch/arm/isa/insts/branch.isa | 4 +-
src/arch/arm/isa/insts/data.isa | 156 +++---
src/arch/arm/isa/insts/div.isa | 16 +-
src/arch/arm/isa/insts/fp.isa | 284 +++++-----
src/arch/arm/isa/insts/ldr.isa | 16 +-
src/arch/arm/isa/insts/macromem.isa | 66 +-
src/arch/arm/isa/insts/mem.isa | 8 +-
src/arch/arm/isa/insts/misc.isa | 8 +-
src/arch/arm/isa/insts/mult.isa | 160 +++---
src/arch/arm/isa/insts/neon.isa | 118 ++--
src/arch/arm/isa/insts/str.isa | 16 +-
src/arch/arm/isa/insts/swap.isa | 6 +-
src/arch/isa_parser.py | 16 +-
src/arch/mips/isa/decoder.isa | 844 +++++++++++++++++-----------------
src/arch/mips/isa/formats/fp.isa | 36 +-
src/arch/mips/isa/formats/int.isa | 4 +-
src/arch/mips/isa/formats/mem.isa | 2 +-
src/arch/power/isa/decoder.isa | 136 ++--
src/arch/power/isa/formats/fp.isa | 4 +-
src/arch/sparc/isa/base.isa | 8 +-
src/arch/sparc/isa/decoder.isa | 362 +++++++-------
src/arch/x86/isa/microops/fpop.isa | 6 +-
src/arch/x86/isa/microops/ldstop.isa | 4 +-
src/arch/x86/isa/microops/limmop.isa | 2 +-
src/arch/x86/isa/microops/mediaop.isa | 218 ++++----
src/arch/x86/isa/microops/regop.isa | 4 +-
29 files changed, 1386 insertions(+), 1386 deletions(-)
diffs (truncated from 6850 to 300 lines):
diff -r acce52081b45 -r ef28ed90449d src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Mon Sep 26 12:18:32 2011 -0500
+++ b/src/arch/alpha/isa/decoder.isa Mon Sep 26 23:48:54 2011 -0700
@@ -41,35 +41,35 @@
}
format LoadOrNop {
- 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
- 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
- 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7;
}});
- 0x23: ldt({{ Fa = Mem.df; }});
- 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
- 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
+ 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
+ 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
+ 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7;
}});
+ 0x23: ldt({{ Fa = Mem_df; }});
+ 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
+ 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
}
format LoadOrPrefetch {
- 0x28: ldl({{ Ra.sl = Mem.sl; }});
- 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
+ 0x28: ldl({{ Ra_sl = Mem_sl; }});
+ 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
// IsFloating flag on lds gets the prefetch to disassemble
// using f31 instead of r31... funcitonally it's unnecessary
- 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
+ 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
}
format Store {
- 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
- 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
- 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
- 0x2d: stq({{ Mem.uq = Ra.uq; }});
- 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
- 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
- 0x27: stt({{ Mem.df = Fa; }});
+ 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
+ 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
+ 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
+ 0x2d: stq({{ Mem_uq = Ra_uq; }});
+ 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
+ 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
+ 0x27: stt({{ Mem_df = Fa; }});
}
format StoreCond {
- 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
+ 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
{{
uint64_t tmp = write_result;
// see stq_c
@@ -78,7 +78,7 @@
xc->setStCondFailures(0);
}
}}, mem_flags = LLSC, inst_flags = IsStoreConditional);
- 0x2f: stq_c({{ Mem.uq = Ra; }},
+ 0x2f: stq_c({{ Mem_uq = Ra; }},
{{
uint64_t tmp = write_result;
// If the write operation returns 0 or 1, then
@@ -102,17 +102,17 @@
0x10: decode INTFUNC { // integer arithmetic operations
- 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
+ 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
0x40: addlv({{
- int32_t tmp = Ra.sl + Rb_or_imm.sl;
+ int32_t tmp = Ra_sl + Rb_or_imm_sl;
// signed overflow occurs when operands have same sign
// and sign of result does not match.
- if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
+ if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
fault = new IntegerOverflowFault;
- Rc.sl = tmp;
+ Rc_sl = tmp;
}});
- 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
- 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
+ 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
+ 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
0x20: addq({{ Rc = Ra + Rb_or_imm; }});
0x60: addqv({{
@@ -126,19 +126,19 @@
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
- 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
+ 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
0x49: sublv({{
- int32_t tmp = Ra.sl - Rb_or_imm.sl;
+ int32_t tmp = Ra_sl - Rb_or_imm_sl;
// signed overflow detection is same as for add,
// except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
- if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
+ if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
fault = new IntegerOverflowFault;
- Rc.sl = tmp;
+ Rc_sl = tmp;
}});
- 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
- 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
+ 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
+ 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
0x29: subq({{ Rc = Ra - Rb_or_imm; }});
0x69: subqv({{
@@ -155,17 +155,17 @@
0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
- 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
- 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
- 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
- 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
+ 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
+ 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
+ 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
+ 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
0x0f: cmpbge({{
int hi = 7;
int lo = 0;
uint64_t tmp = 0;
for (int i = 0; i < 8; ++i) {
- tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
+ tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
hi += 8;
lo += 8;
}
@@ -187,10 +187,10 @@
0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
- 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
- 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
- 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
- 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
+ 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
+ 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
+ 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
+ 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
// For AMASK, RA must be R31.
0x61: decode RA {
@@ -214,8 +214,8 @@
0x12: decode INTFUNC {
0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
- 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
- 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
+ 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
+ 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
@@ -235,10 +235,10 @@
Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
}});
- 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
- 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
- 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
- 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
+ 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
+ 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
+ 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
+ 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
0x5a: extwh({{
Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
@@ -254,15 +254,15 @@
0x57: inswh({{
int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
+ Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
}});
0x67: inslh({{
int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
+ Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
}});
0x77: insqh({{
int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
+ Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
}});
0x30: zap({{
@@ -284,7 +284,7 @@
}
0x13: decode INTFUNC { // integer multiplies
- 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
+ 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{
uint64_t hi, lo;
@@ -293,8 +293,8 @@
}}, IntMultOp);
0x40: mullv({{
// 32-bit multiply with trap on overflow
- int64_t Rax = Ra.sl; // sign extended version of Ra.sl
- int64_t Rbx = Rb_or_imm.sl;
+ int64_t Rax = Ra_sl; // sign extended version of Ra_sl
+ int64_t Rbx = Rb_or_imm_sl;
int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as
@@ -302,7 +302,7 @@
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
fault = new IntegerOverflowFault;
- Rc.sl = tmp<31:0>;
+ Rc_sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
// 64-bit multiply with trap on overflow
@@ -318,8 +318,8 @@
}
0x1c: decode INTFUNC {
- 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
- 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
+ 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
+ 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
0x30: ctpop({{
uint64_t count = 0;
@@ -335,8 +335,8 @@
int hi = 7;
int lo = 0;
for (int i = 0; i < 8; ++i) {
- uint8_t ra_ub = Ra.uq<hi:lo>;
- uint8_t rb_ub = Rb.uq<hi:lo>;
+ uint8_t ra_ub = Ra_uq<hi:lo>;
+ uint8_t rb_ub = Rb_uq<hi:lo>;
temp += (ra_ub >= rb_ub) ?
(ra_ub - rb_ub) : (rb_ub - ra_ub);
hi += 8;
@@ -375,25 +375,25 @@
0x34: unpkbw({{
- Rc = (Rb.uq<7:0>
- | (Rb.uq<15:8> << 16)
- | (Rb.uq<23:16> << 32)
- | (Rb.uq<31:24> << 48));
+ Rc = (Rb_uq<7:0>
+ | (Rb_uq<15:8> << 16)
+ | (Rb_uq<23:16> << 32)
+ | (Rb_uq<31:24> << 48));
}}, IntAluOp);
0x35: unpkbl({{
- Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32));
+ Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
}}, IntAluOp);
0x36: pkwb({{
- Rc = (Rb.uq<7:0>
- | (Rb.uq<23:16> << 8)
- | (Rb.uq<39:32> << 16)
- | (Rb.uq<55:48> << 24));
+ Rc = (Rb_uq<7:0>
+ | (Rb_uq<23:16> << 8)
+ | (Rb_uq<39:32> << 16)
+ | (Rb_uq<55:48> << 24));
}}, IntAluOp);
0x37: pklb({{
- Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8));
+ Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
}}, IntAluOp);
0x38: minsb8({{
@@ -401,11 +401,11 @@
int hi = 63;
int lo = 56;
for (int i = 7; i >= 0; --i) {
- int8_t ra_sb = Ra.uq<hi:lo>;
- int8_t rb_sb = Rb.uq<hi:lo>;
+ int8_t ra_sb = Ra_uq<hi:lo>;
+ int8_t rb_sb = Rb_uq<hi:lo>;
temp = ((temp << 8)
- | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
- : Rb.uq<hi:lo>));
+ | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
hi -= 8;
lo -= 8;
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