The instruction in this context is the load part of a locked CMPXCHG. Its
sequence number is 8916. I kind of know what the control flow is.
Apparently Ruby already has some request that is aliased with this request
and the request is not serviced. The O3 CPU then starts squashing
everything and this instruction raises the assert. Given that this
instruction is a memory barrier, I am not sure why the load request was
issued in first place.
Here are some snippets from the O3CPU trace --
7383000: system.cpu0.iew: IQ has 44 free entries (Can schedule: 0). LSQ
has 27 free entries.
7383000: system.cpu0.commit: Getting instructions from Rename stage.
7383000: system.cpu0.commit: Trying to commit instructions in the ROB.
7383000: system.cpu0.commit: Trying to commit head instruction, [sn:8916]
[tid:0]
7383000: system.cpu0.commit: Encountered a barrier or non-speculative
instruction [sn:8916] at the head of the ROB, PC
(0x41c7d6=>0x41c7de).(1=>2).
7383000: system.cpu0.commit: Waiting for all stores to writeback.
7383000: system.cpu0.commit: Unable to commit head instruction
PC:(0x41c7d6=>0x41c7de).(1=>2) [tid:0] [sn:8916].
7383000: system.cpu0.commit: [tid:0]: Instruction [sn:8916] PC
(0x41c7d6=>0x41c7de).(1=>2) is head of ROB and ready to commit
7383000: system.cpu0.commit: [tid:0]: ROB has 51 insts & 141 free entries.
.
.
.
7383500: system.cpu0.iew: IQ has 44 free entries (Can schedule: 0). LSQ
has 28 free entries.
7383500: system.cpu0.iew: Activity this cycle.
7383500: system.cpu0.commit: Getting instructions from Rename stage.
7383500: system.cpu0.commit: Trying to commit instructions in the ROB.
7383500: system.cpu0.commit: Trying to commit head instruction, [sn:8916]
[tid:0]
7383500: system.cpu0.commit: Encountered a barrier or non-speculative
instruction [sn:8916] at the head of the ROB, PC
(0x41c7d6=>0x41c7de).(1=>2).
7383500: system.cpu0.commit: Unable to commit head instruction
PC:(0x41c7d6=>0x41c7de).(1=>2) [tid:0] [sn:8916].
7383500: system.cpu0.commit: [tid:0]: Can't commit, Instruction [sn:8916]
PC (0x41c7d6=>0x41c7de).(1=>2) is head of ROB and not ready
.
.
.
7384000: system.cpu0.iq: Marking nonspeculative instruction [sn:8916] as
ready to execute.
7384000: system.cpu0.memDep0: Marking non speculative instruction PC
(0x41c7d6=>0x41c7de).(1=>2) as ready [sn:8916].
7384000: system.cpu0.memDep0: Adding instruction [sn:8916] to the ready
list.
7384000: system.cpu0.iq: Instruction is ready to issue, putting it onto
the ready list, PC (0x41c7d6=>0x41c7de).(1=>2) opclass:30 [sn:8916].
7384000: system.cpu0.iew: [tid:0], Dispatch dispatched 0 instructions.
7384000: system.cpu0.iew: IQ has 44 free entries (Can schedule: 1). LSQ
has 28 free entries.
7384000: system.cpu0.iew: IEW switching to active
7384000: system.cpu0.iew: Activating stage.
7384000: system.cpu0: Activity: 2
7384000: system.cpu0.commit: Getting instructions from Rename stage.
7384000: system.cpu0.commit: Trying to commit instructions in the ROB.
7384000: system.cpu0.commit: [tid:0]: Can't commit, Instruction [sn:8916]
PC (0x41c7d6=>0x41c7de).(1=>2) is head of ROB and not ready
.
.
.
7384500: system.cpu0.iq: Thread 0: Issuing instruction PC
(0x41c7d6=>0x41c7de).(1=>2) [sn:8916]
7384500: system.cpu0.memDep0: Issuing instruction PC 0x41c7d6 [sn:8916].
.
.
.
7385000: system.cpu0.iew: Execute: Executing instructions from IQ.
7385000: system.cpu0.iew: Execute: Processing PC
(0x41c7d6=>0x41c7de).(1=>2), [tid:0] [sn:8916].
7385000: system.cpu0.iew: Execute: Calculating address for memory
reference.
7385000: system.cpu0.iew.lsq.thread0: Executing load PC
(0x41c7d6=>0x41c7de).(1=>2), [sn:8916]
7385000: global: RegFile: Access to int register 16, has data 0
7385000: global: RegFile: Access to int register 102, has data 0x41c7de
7385000: system.cpu0.iew.lsq.thread0: Read called, load idx: 12, store
idx: 16, storeHead: 16 addr: 0x93f40
7385000: system.cpu0.iew.lsq.thread0: Doing memory access for inst
[sn:8916] PC (0x41c7d6=>0x41c7de).(1=>2)
7385000: system.l1_cntrl0.sequencer-port1: Timing access caught for
address 0x93f40
7385000: system.l1_cntrl0.sequencer-port1: Request found in 0 - 0x1fffffff
range
7385000: system.l1_cntrl0.sequencer-port1: Issuing Locked RMW Read
7385000: system.l1_cntrl0.sequencer-port1: Request for address 0x93f40 did
not issue because Aliased
7385000: system.cpu0.iew: wbOutstanding: 2 [sn:8916]
7385000: system.cpu0.iew: Load operation couldn't execute because the
memory system is blocked. PC: (0x41c7d6=>0x41c7de).(1=>2) [sn:8916]
7385000: system.cpu0.iew: [tid:0]: Memory blocked, squashing load and
younger insts, PC: (0x41c7d6=>0x41c7de).(1=>2) [sn:8916].
.
.
.
7385500: system.cpu0.commit: [tid:0]: Squashing due to order violation
[sn:8916]
7385500: system.cpu0.commit: [tid:0]: Redirecting to PC 0x41c7de
7385500: system.cpu0.rob: Starting to squash within the ROB.
7385500: system.cpu0.rob: [tid:0]: Squashing instructions until [sn:8915].
--
Nilay
On Mon, 31 Oct 2011, Korey Sewell wrote:
Seems like the non-spec, mem. barrier inst has a fault.
Can you identify what fault it is (inst->getFault()->name())?
Also, what's the "Commit" debug flag trace say on the tick where the CPU
decides it can't commit that particular instruction?
On Mon, Oct 31, 2011 at 1:13 PM, Nilay Vaish <[email protected]> wrote:
Hello
I am observing a peculiar behavior while running the O3 CPU. There is a
non-speculative, memory barrier instruction at the head of the ROB. The ROB
waits for many ticks to write back all the stores before this instruction.
Then all of a sudden, in of the ticks, the CPU decides that it cannot
commit this particular instruction and then it decides to squash this
instruction. Can some one explain as to why this might happen?
While squashing the instruction, the following code from the function
doSquash() in o3/inst_queue_impl.hh is invoked. That particular instruction
fails on the assert. If I comment out the assert, the simulation runs to
completion (which is indicator of nothing). Should this instruction fail
this assert? How can I ensure that the simulation runs fine even when the
assert is in place?
} else if (!squashed_inst->**isStoreConditional() ||
!squashed_inst->isCompleted()) {
NonSpecMapIt ns_inst_it =
nonSpecInsts.find(squashed_**inst->seqNum);
if (ns_inst_it == nonSpecInsts.end()) {
assert(squashed_inst->**getFault() != NoFault);
} else {
(*ns_inst_it).second = NULL;
nonSpecInsts.erase(ns_inst_it)**;
++iqSquashedNonSpecRemoved;
}
}
Note that I am running O3 CPU with Ruby.
Thanks
Nilay
______________________________**_________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/**listinfo/gem5-dev<http://m5sim.org/mailman/listinfo/gem5-dev>
--
- Korey
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
