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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- O3: Remove hardcoded tgts_per_mshr in O3CPU.py. There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. Diffs ----- configs/common/Caches.py 5fb918115c07 src/cpu/o3/O3CPU.py 5fb918115c07 Diff: http://reviews.m5sim.org/r/906/diff Testing ------- Thanks, Ali _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
