changeset e66a566f2cfa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e66a566f2cfa
description:
Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest.
This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of
RubyRequest.
diffstat:
src/mem/SConscript | 5 +-
src/mem/ruby/recorder/TraceRecord.cc | 8 +-
src/mem/ruby/system/DMASequencer.cc | 23 +-
src/mem/ruby/system/DMASequencer.hh | 2 +-
src/mem/ruby/system/RubyPort.cc | 72 +------
src/mem/ruby/system/RubyPort.hh | 2 +-
src/mem/ruby/system/Sequencer.cc | 378 +++++++++++++++++-----------------
src/mem/ruby/system/Sequencer.hh | 17 +-
8 files changed, 209 insertions(+), 298 deletions(-)
diffs (truncated from 832 to 300 lines):
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/SConscript
--- a/src/mem/SConscript Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/SConscript Mon Nov 14 17:44:35 2011 -0600
@@ -68,10 +68,11 @@
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
DebugFlag('RubyQueue')
+DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
DebugFlag('RubyStorebuffer')
DebugFlag('RubyTester')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
- 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',
- 'RubyMemory', 'RubyDma', 'RubyPort'])
+ 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',
+ 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer'])
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/ruby/recorder/TraceRecord.cc
--- a/src/mem/ruby/recorder/TraceRecord.cc Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/ruby/recorder/TraceRecord.cc Mon Nov 14 17:44:35 2011 -0600
@@ -73,17 +73,15 @@
TraceRecord::issueRequest() const
{
assert(m_sequencer_ptr != NULL);
-
- RubyRequest request(m_data_address.getAddress(), NULL,
- RubySystem::getBlockSizeBytes(), m_pc_address.getAddress(),
- m_type, RubyAccessMode_User, NULL);
+ Request req(m_data_address.getAddress(), 0, 0);
+ Packet *pkt = new Packet(&req, MemCmd(MemCmd::InvalidCmd), -1);
// Clear out the sequencer
while (!m_sequencer_ptr->empty()) {
g_eventQueue_ptr->triggerEvents(g_eventQueue_ptr->getTime() + 100);
}
- m_sequencer_ptr->makeRequest(request);
+ m_sequencer_ptr->makeRequest(pkt);
// Clear out the sequencer
while (!m_sequencer_ptr->empty()) {
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/ruby/system/DMASequencer.cc Mon Nov 14 17:44:35 2011 -0600
@@ -48,27 +48,16 @@
}
RequestStatus
-DMASequencer::makeRequest(const RubyRequest &request)
+DMASequencer::makeRequest(PacketPtr pkt)
{
if (m_is_busy) {
return RequestStatus_BufferFull;
}
- uint64_t paddr = request.m_PhysicalAddress.getAddress();
- uint8_t* data = request.data;
- int len = request.m_Size;
- bool write = false;
- switch(request.m_Type) {
- case RubyRequestType_LD:
- write = false;
- break;
- case RubyRequestType_ST:
- write = true;
- break;
- default:
- panic("DMASequencer::makeRequest does not support RubyRequestType");
- return RequestStatus_NULL;
- }
+ uint64_t paddr = pkt->getAddr();
+ uint8_t* data = pkt->getPtr<uint8_t>(true);
+ int len = pkt->getSize();
+ bool write = pkt->isWrite();
assert(!m_is_busy); // only support one outstanding DMA request
m_is_busy = true;
@@ -79,7 +68,7 @@
active_request.len = len;
active_request.bytes_completed = 0;
active_request.bytes_issued = 0;
- active_request.pkt = request.pkt;
+ active_request.pkt = pkt;
SequencerMsg *msg = new SequencerMsg;
msg->getPhysicalAddress() = Address(paddr);
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/ruby/system/DMASequencer.hh
--- a/src/mem/ruby/system/DMASequencer.hh Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/ruby/system/DMASequencer.hh Mon Nov 14 17:44:35 2011 -0600
@@ -53,7 +53,7 @@
DMASequencer(const Params *);
void init();
/* external interface */
- RequestStatus makeRequest(const RubyRequest & request);
+ RequestStatus makeRequest(PacketPtr pkt);
bool busy() { return m_is_busy;}
/* SLICC callback */
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.cc Mon Nov 14 17:44:35 2011 -0600
@@ -26,10 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "config/the_isa.hh"
-#if THE_ISA == X86_ISA
-#include "arch/x86/insts/microldstop.hh"
-#endif // X86_ISA
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/Ruby.hh"
#include "mem/protocol/AccessPermission.hh"
@@ -199,73 +195,11 @@
return ruby_port->pio_port->sendTiming(pkt);
}
- // For DMA and CPU requests, translate them to ruby requests before
- // sending them to our assigned ruby port.
- RubyRequestType type = RubyRequestType_NULL;
-
- // If valid, copy the pc to the ruby request
- Addr pc = 0;
- if (pkt->req->hasPC()) {
- pc = pkt->req->getPC();
- }
-
- if (pkt->isLLSC()) {
- if (pkt->isWrite()) {
- DPRINTF(RubyPort, "Issuing SC\n");
- type = RubyRequestType_Store_Conditional;
- } else {
- DPRINTF(RubyPort, "Issuing LL\n");
- assert(pkt->isRead());
- type = RubyRequestType_Load_Linked;
- }
- } else if (pkt->req->isLocked()) {
- if (pkt->isWrite()) {
- DPRINTF(RubyPort, "Issuing Locked RMW Write\n");
- type = RubyRequestType_Locked_RMW_Write;
- } else {
- DPRINTF(RubyPort, "Issuing Locked RMW Read\n");
- assert(pkt->isRead());
- type = RubyRequestType_Locked_RMW_Read;
- }
- } else {
- if (pkt->isRead()) {
- if (pkt->req->isInstFetch()) {
- type = RubyRequestType_IFETCH;
- } else {
-#if THE_ISA == X86_ISA
- uint32_t flags = pkt->req->getFlags();
- bool storeCheck = flags &
- (TheISA::StoreCheck << TheISA::FlagShift);
-#else
- bool storeCheck = false;
-#endif // X86_ISA
- if (storeCheck) {
- type = RubyRequestType_RMW_Read;
- } else {
- type = RubyRequestType_LD;
- }
- }
- } else if (pkt->isWrite()) {
- //
- // Note: M5 packets do not differentiate ST from RMW_Write
- //
- type = RubyRequestType_ST;
- } else if (pkt->isFlush()) {
- type = RubyRequestType_FLUSH;
- } else {
- panic("Unsupported ruby packet type\n");
- }
- }
-
- RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(true),
- pkt->getSize(), pc, type,
- RubyAccessMode_Supervisor, pkt);
-
- assert(ruby_request.m_PhysicalAddress.getOffset() + ruby_request.m_Size <=
- RubySystem::getBlockSizeBytes());
+ assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
+ RubySystem::getBlockSizeBytes());
// Submit the ruby request
- RequestStatus requestStatus = ruby_port->makeRequest(ruby_request);
+ RequestStatus requestStatus = ruby_port->makeRequest(pkt);
// If the request successfully issued then we should return true.
// Otherwise, we need to delete the senderStatus we just created and return
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/ruby/system/RubyPort.hh
--- a/src/mem/ruby/system/RubyPort.hh Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.hh Mon Nov 14 17:44:35 2011 -0600
@@ -114,7 +114,7 @@
Port *getPort(const std::string &if_name, int idx);
- virtual RequestStatus makeRequest(const RubyRequest & request) = 0;
+ virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
//
// Called by the controller to give the sequencer a pointer.
diff -r 2fc7787f47a9 -r e66a566f2cfa src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Wed Nov 09 21:48:28 2011 -0800
+++ b/src/mem/ruby/system/Sequencer.cc Mon Nov 14 17:44:35 2011 -0600
@@ -28,15 +28,21 @@
#include "base/misc.hh"
#include "base/str.hh"
+#include "config/the_isa.hh"
+#if THE_ISA == X86_ISA
+#include "arch/x86/insts/microldstop.hh"
+#endif // X86_ISA
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/MemoryAccess.hh"
#include "debug/ProtocolTrace.hh"
+#include "debug/RubySequencer.hh"
+#include "mem/protocol/PrefetchBit.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/recorder/Tracer.hh"
-#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/CacheMemory.hh"
#include "mem/ruby/system/Sequencer.hh"
@@ -62,7 +68,6 @@
m_outstanding_count = 0;
- m_max_outstanding_requests = 0;
m_deadlock_threshold = 0;
m_instCache_ptr = NULL;
m_dataCache_ptr = NULL;
@@ -103,7 +108,7 @@
panic("Possible Deadlock detected. Aborting!\n"
"version: %d request.paddr: 0x%x m_readRequestTable: %d "
"current time: %u issue_time: %d difference: %d\n", m_version,
- request->ruby_request.m_PhysicalAddress,
m_readRequestTable.size(),
+ Address(request->pkt->getAddr()), m_readRequestTable.size(),
current_time, request->issue_time,
current_time - request->issue_time);
}
@@ -118,7 +123,7 @@
panic("Possible Deadlock detected. Aborting!\n"
"version: %d request.paddr: 0x%x m_writeRequestTable: %d "
"current time: %u issue_time: %d difference: %d\n", m_version,
- request->ruby_request.m_PhysicalAddress,
m_writeRequestTable.size(),
+ Address(request->pkt->getAddr()), m_writeRequestTable.size(),
current_time, request->issue_time,
current_time - request->issue_time);
}
@@ -213,8 +218,8 @@
// Insert the request on the correct request table. Return true if
// the entry was already present.
-bool
-Sequencer::insertRequest(SequencerRequest* request)
+RequestStatus
+Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
{
int total_outstanding =
m_writeRequestTable.size() + m_readRequestTable.size();
@@ -226,52 +231,64 @@
schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
}
- Address line_addr(request->ruby_request.m_PhysicalAddress);
+ Address line_addr(pkt->getAddr());
line_addr.makeLineAddress();
- if ((request->ruby_request.m_Type == RubyRequestType_ST) ||
- (request->ruby_request.m_Type == RubyRequestType_ATOMIC) ||
- (request->ruby_request.m_Type == RubyRequestType_RMW_Read) ||
- (request->ruby_request.m_Type == RubyRequestType_RMW_Write) ||
- (request->ruby_request.m_Type == RubyRequestType_Load_Linked) ||
- (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) ||
- (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) ||
- (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) ||
- (request->ruby_request.m_Type == RubyRequestType_FLUSH)) {
+ if ((request_type == RubyRequestType_ST) ||
+ (request_type == RubyRequestType_RMW_Read) ||
+ (request_type == RubyRequestType_RMW_Write) ||
+ (request_type == RubyRequestType_Load_Linked) ||
+ (request_type == RubyRequestType_Store_Conditional) ||
+ (request_type == RubyRequestType_Locked_RMW_Read) ||
+ (request_type == RubyRequestType_Locked_RMW_Write) ||
+ (request_type == RubyRequestType_FLUSH)) {
+
+ // Check if there is any outstanding read request for the same
+ // cache line.
+ if (m_readRequestTable.count(line_addr) > 0) {
+ m_store_waiting_on_load_cycles++;
+ return RequestStatus_Aliased;
+ }
+
pair<RequestTable::iterator, bool> r =
m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
- bool success = r.second;
- RequestTable::iterator i = r.first;
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