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When you upload a new review, be sure to update the old one. That way you can see what changed between revisions. src/cpu/base_dyn_inst.hh <http://reviews.m5sim.org/r/910/#comment2167> Like I said before, you shouldn't use this instResult mechanism. It's broken and obsolete and needs to be removed all together. src/cpu/o3/thread_context.hh <http://reviews.m5sim.org/r/910/#comment2169> These shouldn't be squished all onto one line. src/cpu/thread_context.hh <http://reviews.m5sim.org/r/910/#comment2168> I think all of these new functions could be replaced with a getCheckerCPU call on the base CPU class. Then you can get the TLB pointers from it and even factor some of the code that's duplicated for the checker into functions that take a CPU pointer. src/mem/packet.hh <http://reviews.m5sim.org/r/910/#comment2170> I still don't see the point of this. The memory system should be taking care of this, and it shouldn't have anything to do with the checker. - Gabe On 2011-11-23 15:07:45, Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/910/ > ----------------------------------------------------------- > > (Updated 2011-11-23 15:07:45) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > build_opts/ARM_wCHECKER_FS PRE-CREATION > build_opts/ARM_wCHECKER_SE PRE-CREATION > src/arch/arm/isa.cc 62dee0c98d53 > src/arch/arm/isa/insts/m5ops.isa 62dee0c98d53 > src/arch/arm/isa/insts/misc.isa 62dee0c98d53 > src/arch/arm/table_walker.hh 62dee0c98d53 > src/arch/arm/table_walker.cc 62dee0c98d53 > src/arch/arm/tlb.hh 62dee0c98d53 > src/arch/arm/tlb.cc 62dee0c98d53 > src/arch/arm/utility.cc 62dee0c98d53 > src/cpu/BaseCPU.py 62dee0c98d53 > src/cpu/CheckerCPU.py 62dee0c98d53 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/SConscript 62dee0c98d53 > src/cpu/base.cc 62dee0c98d53 > src/cpu/base_dyn_inst.hh 62dee0c98d53 > src/cpu/base_dyn_inst_impl.hh 62dee0c98d53 > src/cpu/checker/cpu.hh 62dee0c98d53 > src/cpu/checker/cpu.cc 62dee0c98d53 > src/cpu/checker/cpu_impl.hh 62dee0c98d53 > src/cpu/checker/thread_context.hh 62dee0c98d53 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py 62dee0c98d53 > src/cpu/o3/O3Checker.py 62dee0c98d53 > src/cpu/o3/checker_builder.cc 62dee0c98d53 > src/cpu/o3/commit_impl.hh 62dee0c98d53 > src/cpu/o3/cpu.hh 62dee0c98d53 > src/cpu/o3/cpu.cc 62dee0c98d53 > src/cpu/o3/dyn_inst_impl.hh 62dee0c98d53 > src/cpu/o3/fetch_impl.hh 62dee0c98d53 > src/cpu/o3/iew_impl.hh 62dee0c98d53 > src/cpu/o3/lsq_unit_impl.hh 62dee0c98d53 > src/cpu/o3/thread_context.hh 62dee0c98d53 > src/cpu/o3/thread_context_impl.hh 62dee0c98d53 > src/cpu/simple/BaseSimpleCPU.py 62dee0c98d53 > src/cpu/simple/base.hh 62dee0c98d53 > src/cpu/simple/base.cc 62dee0c98d53 > src/cpu/simple_thread.hh 62dee0c98d53 > src/cpu/thread_context.hh 62dee0c98d53 > src/mem/bus.cc 62dee0c98d53 > src/mem/packet.hh 62dee0c98d53 > src/mem/packet.cc 62dee0c98d53 > > Diff: http://reviews.m5sim.org/r/910/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
