changeset 7a5780ab74d7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a5780ab74d7
description:
ARM: Add support for having a TLB cache.
diffstat:
src/cpu/BaseCPU.py | 19 ++++++++++---------
1 files changed, 10 insertions(+), 9 deletions(-)
diffs (29 lines):
diff -r 613a69fe1d98 -r 7a5780ab74d7 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Thu Dec 01 00:15:22 2011 -0800
+++ b/src/cpu/BaseCPU.py Thu Dec 01 00:15:22 2011 -0800
@@ -182,15 +182,16 @@
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['FULL_SYSTEM']:
- if buildEnv['TARGET_ISA'] == 'x86':
- self.itb_walker_cache = iwc
- self.dtb_walker_cache = dwc
- self.itb.walker.port = iwc.cpu_side
- self.dtb.walker.port = dwc.cpu_side
- self._cached_ports += ["itb_walker_cache.mem_side", \
- "dtb_walker_cache.mem_side"]
- elif buildEnv['TARGET_ISA'] == 'arm':
- self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ if iwc and dwc:
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
+ else:
+ self._cached_ports += ["itb.walker.port",
"dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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