> On 2011-12-07 15:47:00, Brad Beckmann wrote: > > Thanks for pushing this forward Nilay! I will feel very good to see this > > functionality finally checked in. I know people are concerned about the > > eventq manipulation, but what Nilay has implemented is much better than > > some of our other suggestions. As a result of this change, we can start > > the process of removing all the files in src/mem/ruby/eventqueue. That > > will be very nice. > > > > My two biggest concerns are the global variables and not utilizing the > > recently added cache flush support to create valid data checkpoints of both > > the caches and memory. See comments below.
Well, at least we're making the best of a presumably not so great situation. It does sound like a good idea to get rid of a parallel implementation of the event queue, but weren't we trying to have multiple queues for the parallelization work? If so, maybe we can have two instances of the same class and avoid the sneaky tricks. We may not be ready for that today, but it sounds like a decent longer term goal. In any case, I'm glad to see things improve even if we don't/can't go directly to an ideal solution. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/927/#review1744 ----------------------------------------------------------- On 2011-12-05 08:09:50, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/927/ > ----------------------------------------------------------- > > (Updated 2011-12-05 08:09:50) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Ruby: Resurrect Cache Warmup Capability > This patch resurrects ruby's cache warmup capability. > > > Diffs > ----- > > configs/ruby/MOESI_hammer.py c1ab57ea8805 > configs/ruby/Ruby.py c1ab57ea8805 > src/mem/SConscript c1ab57ea8805 > src/mem/protocol/MOESI_CMP_token-L1cache.sm c1ab57ea8805 > src/mem/protocol/MOESI_CMP_token-L2cache.sm c1ab57ea8805 > src/mem/protocol/MOESI_CMP_token-dir.sm c1ab57ea8805 > src/mem/protocol/MOESI_hammer-cache.sm c1ab57ea8805 > src/mem/protocol/MOESI_hammer-dir.sm c1ab57ea8805 > src/mem/ruby/buffers/MessageBuffer.cc c1ab57ea8805 > src/mem/ruby/common/Global.hh c1ab57ea8805 > src/mem/ruby/common/Global.cc c1ab57ea8805 > src/mem/ruby/eventqueue/RubyEventQueue.hh c1ab57ea8805 > src/mem/ruby/eventqueue/RubyEventQueue.cc c1ab57ea8805 > src/mem/ruby/network/Network.hh c1ab57ea8805 > src/mem/ruby/network/Network.cc c1ab57ea8805 > src/mem/ruby/network/Topology.cc c1ab57ea8805 > src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc c1ab57ea8805 > src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc > c1ab57ea8805 > src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc c1ab57ea8805 > src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc c1ab57ea8805 > src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc c1ab57ea8805 > src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc > c1ab57ea8805 > src/mem/ruby/network/garnet/flexible-pipeline/Router.cc c1ab57ea8805 > src/mem/ruby/network/simple/PerfectSwitch.cc c1ab57ea8805 > src/mem/ruby/network/simple/SimpleNetwork.cc c1ab57ea8805 > src/mem/ruby/network/simple/Switch.cc c1ab57ea8805 > src/mem/ruby/network/simple/Throttle.cc c1ab57ea8805 > src/mem/ruby/recorder/CacheRecorder.hh c1ab57ea8805 > src/mem/ruby/recorder/CacheRecorder.cc c1ab57ea8805 > src/mem/ruby/recorder/SConscript c1ab57ea8805 > src/mem/ruby/recorder/TraceRecord.hh c1ab57ea8805 > src/mem/ruby/recorder/TraceRecord.cc c1ab57ea8805 > src/mem/ruby/recorder/Tracer.hh c1ab57ea8805 > src/mem/ruby/recorder/Tracer.cc c1ab57ea8805 > src/mem/ruby/recorder/Tracer.py c1ab57ea8805 > src/mem/ruby/slicc_interface/AbstractController.hh c1ab57ea8805 > src/mem/ruby/slicc_interface/AbstractController.cc c1ab57ea8805 > src/mem/ruby/system/Cache.py c1ab57ea8805 > src/mem/ruby/system/CacheMemory.hh c1ab57ea8805 > src/mem/ruby/system/CacheMemory.cc c1ab57ea8805 > src/mem/ruby/system/DMASequencer.hh c1ab57ea8805 > src/mem/ruby/system/MemoryControl.hh c1ab57ea8805 > src/mem/ruby/system/MemoryControl.cc c1ab57ea8805 > src/mem/ruby/system/RubyPort.hh c1ab57ea8805 > src/mem/ruby/system/RubyPort.cc c1ab57ea8805 > src/mem/ruby/system/SConscript c1ab57ea8805 > src/mem/ruby/system/Sequencer.hh c1ab57ea8805 > src/mem/ruby/system/Sequencer.cc c1ab57ea8805 > src/mem/ruby/system/System.hh c1ab57ea8805 > src/mem/ruby/system/System.cc c1ab57ea8805 > src/mem/slicc/symbols/StateMachine.py c1ab57ea8805 > src/sim/eventq.hh c1ab57ea8805 > > Diff: http://reviews.m5sim.org/r/927/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
