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Review request for Default and Gabe Black. Summary ------- This is a squashed diff of my merged repository with patches applied and the main repository. I created it by merging the two in my repository, applying the patches, and running this command: hg diff -r c1ab57ea8805 -r qtip --exclude 'glob:tests/quick/*' --exclude 'glob:tests/long/*' > sefsmergesquashed.patch The massive diff produced earlier, in addition to being backwards, did not exclude moving around the test stuff. Imagine that there's now an se and fs sub dir under long and quick, and that things were moved into them as appropriate. I sent an email a while ago with the output of running quick regressions on the repository in this state, so you should be able to look at that to get an idea what's happening in the parts I'm leaving out. I have yet to measure how performance changes with when SE vs. FS is a run time decision, but since I don't remember it coming up in performance critical areas and those branches should be extremely predictable, I don't expect there to be much of a change. Diffs ----- SConstruct c1ab57ea8805 build_opts/ALPHA PRE-CREATION build_opts/ALPHA_FS c1ab57ea8805 build_opts/ALPHA_MESI_CMP_directory PRE-CREATION build_opts/ALPHA_MOESI_CMP_directory PRE-CREATION build_opts/ALPHA_MOESI_CMP_token PRE-CREATION build_opts/ALPHA_MOESI_hammer PRE-CREATION build_opts/ALPHA_Network_test PRE-CREATION build_opts/ALPHA_SE c1ab57ea8805 build_opts/ALPHA_SE_MESI_CMP_directory c1ab57ea8805 build_opts/ALPHA_SE_MOESI_CMP_directory c1ab57ea8805 build_opts/ALPHA_SE_MOESI_CMP_token c1ab57ea8805 build_opts/ALPHA_SE_MOESI_hammer c1ab57ea8805 build_opts/ALPHA_SE_Network_test c1ab57ea8805 build_opts/ARM PRE-CREATION build_opts/ARM_FS c1ab57ea8805 build_opts/ARM_SE c1ab57ea8805 build_opts/MIPS PRE-CREATION build_opts/MIPS_SE c1ab57ea8805 build_opts/POWER PRE-CREATION build_opts/POWER_SE c1ab57ea8805 build_opts/SPARC PRE-CREATION build_opts/SPARC_FS c1ab57ea8805 build_opts/SPARC_SE c1ab57ea8805 build_opts/X86 PRE-CREATION build_opts/X86_FS c1ab57ea8805 build_opts/X86_SE c1ab57ea8805 configs/common/FSConfig.py c1ab57ea8805 configs/common/Simulation.py c1ab57ea8805 configs/example/fs.py c1ab57ea8805 configs/example/memtest.py c1ab57ea8805 configs/example/ruby_direct_test.py c1ab57ea8805 configs/example/ruby_fs.py c1ab57ea8805 configs/example/ruby_mem_test.py c1ab57ea8805 configs/example/ruby_network_test.py c1ab57ea8805 configs/example/ruby_random_test.py c1ab57ea8805 configs/example/se.py c1ab57ea8805 configs/ruby/Network_test.py c1ab57ea8805 configs/splash2/cluster.py c1ab57ea8805 configs/splash2/run.py c1ab57ea8805 src/arch/alpha/AlphaSystem.py c1ab57ea8805 src/arch/alpha/SConscript c1ab57ea8805 src/arch/alpha/ev5.cc c1ab57ea8805 src/arch/alpha/faults.hh c1ab57ea8805 src/arch/alpha/faults.cc c1ab57ea8805 src/arch/alpha/isa/decoder.isa c1ab57ea8805 src/arch/alpha/isa/fp.isa c1ab57ea8805 src/arch/alpha/isa/main.isa c1ab57ea8805 src/arch/alpha/isa_traits.hh c1ab57ea8805 src/arch/alpha/linux/system.cc c1ab57ea8805 src/arch/alpha/pagetable.hh c1ab57ea8805 src/arch/alpha/predecoder.hh c1ab57ea8805 src/arch/alpha/regredir.cc c1ab57ea8805 src/arch/alpha/remote_gdb.cc c1ab57ea8805 src/arch/alpha/system.hh c1ab57ea8805 src/arch/alpha/system.cc c1ab57ea8805 src/arch/alpha/tlb.cc c1ab57ea8805 src/arch/alpha/utility.hh c1ab57ea8805 src/arch/alpha/utility.cc c1ab57ea8805 src/arch/arm/ArmTLB.py c1ab57ea8805 src/arch/arm/SConscript c1ab57ea8805 src/arch/arm/faults.hh c1ab57ea8805 src/arch/arm/faults.cc c1ab57ea8805 src/arch/arm/insts/static_inst.hh c1ab57ea8805 src/arch/arm/isa/formats/data.isa c1ab57ea8805 src/arch/arm/isa/formats/m5ops.isa c1ab57ea8805 src/arch/arm/isa/formats/unimp.isa c1ab57ea8805 src/arch/arm/isa/insts/div.isa c1ab57ea8805 src/arch/arm/isa/insts/m5ops.isa c1ab57ea8805 src/arch/arm/isa/insts/misc.isa c1ab57ea8805 src/arch/arm/isa/insts/neon.isa c1ab57ea8805 src/arch/arm/isa/insts/swap.isa c1ab57ea8805 src/arch/arm/pagetable.hh c1ab57ea8805 src/arch/arm/remote_gdb.cc c1ab57ea8805 src/arch/arm/tlb.hh c1ab57ea8805 src/arch/arm/tlb.cc c1ab57ea8805 src/arch/arm/utility.cc c1ab57ea8805 src/arch/mips/BISystem.py c1ab57ea8805 src/arch/mips/MipsSystem.py c1ab57ea8805 src/arch/mips/SConscript c1ab57ea8805 src/arch/mips/dsp.hh c1ab57ea8805 src/arch/mips/dsp.cc c1ab57ea8805 src/arch/mips/faults.hh c1ab57ea8805 src/arch/mips/faults.cc c1ab57ea8805 src/arch/mips/interrupts.cc c1ab57ea8805 src/arch/mips/isa/decoder.isa c1ab57ea8805 src/arch/mips/isa/formats/control.isa c1ab57ea8805 src/arch/mips/isa/formats/dsp.isa c1ab57ea8805 src/arch/mips/isa/formats/fp.isa c1ab57ea8805 src/arch/mips/isa/formats/unimp.isa c1ab57ea8805 src/arch/mips/isa/includes.isa c1ab57ea8805 src/arch/mips/isa_traits.hh c1ab57ea8805 src/arch/mips/linux/system.cc c1ab57ea8805 src/arch/mips/mips_core_specific.hh c1ab57ea8805 src/arch/mips/mips_core_specific.cc c1ab57ea8805 src/arch/mips/pagetable.hh c1ab57ea8805 src/arch/mips/remote_gdb.cc c1ab57ea8805 src/arch/mips/stacktrace.cc c1ab57ea8805 src/arch/mips/system.hh c1ab57ea8805 src/arch/mips/system.cc c1ab57ea8805 src/arch/mips/tlb.hh c1ab57ea8805 src/arch/mips/tlb.cc c1ab57ea8805 src/arch/mips/utility.hh c1ab57ea8805 src/arch/mips/utility.cc c1ab57ea8805 src/arch/mips/vtophys.hh c1ab57ea8805 src/arch/mips/vtophys.cc c1ab57ea8805 src/arch/power/PowerInterrupts.py PRE-CREATION src/arch/power/SConscript c1ab57ea8805 src/arch/power/interrupts.hh PRE-CREATION src/arch/power/interrupts.cc PRE-CREATION src/arch/power/kernel_stats.hh PRE-CREATION src/arch/power/pagetable.hh c1ab57ea8805 src/arch/power/stacktrace.cc PRE-CREATION src/arch/power/tlb.cc c1ab57ea8805 src/arch/power/utility.hh c1ab57ea8805 src/arch/power/utility.cc c1ab57ea8805 src/arch/power/vtophys.hh c1ab57ea8805 src/arch/power/vtophys.cc PRE-CREATION src/arch/sparc/SConscript c1ab57ea8805 src/arch/sparc/faults.hh c1ab57ea8805 src/arch/sparc/faults.cc c1ab57ea8805 src/arch/sparc/isa.hh c1ab57ea8805 src/arch/sparc/isa.cc c1ab57ea8805 src/arch/sparc/isa/base.isa c1ab57ea8805 src/arch/sparc/isa/formats/mem/util.isa c1ab57ea8805 src/arch/sparc/isa/includes.isa c1ab57ea8805 src/arch/sparc/isa_traits.hh c1ab57ea8805 src/arch/sparc/mmapped_ipr.hh c1ab57ea8805 src/arch/sparc/pagetable.hh c1ab57ea8805 src/arch/sparc/remote_gdb.cc c1ab57ea8805 src/arch/sparc/tlb.hh c1ab57ea8805 src/arch/sparc/tlb.cc c1ab57ea8805 src/arch/sparc/ua2005.cc c1ab57ea8805 src/arch/sparc/utility.hh c1ab57ea8805 src/arch/sparc/utility.cc c1ab57ea8805 src/arch/x86/SConscript c1ab57ea8805 src/arch/x86/X86LocalApic.py c1ab57ea8805 src/arch/x86/X86TLB.py c1ab57ea8805 src/arch/x86/bios/SConscript c1ab57ea8805 src/arch/x86/faults.hh c1ab57ea8805 src/arch/x86/faults.cc c1ab57ea8805 src/arch/x86/interrupts.hh c1ab57ea8805 src/arch/x86/interrupts.cc c1ab57ea8805 src/arch/x86/isa/decoder/one_byte_opcodes.isa c1ab57ea8805 src/arch/x86/isa/decoder/two_byte_opcodes.isa c1ab57ea8805 src/arch/x86/isa/includes.isa c1ab57ea8805 src/arch/x86/mmapped_ipr.hh c1ab57ea8805 src/arch/x86/remote_gdb.cc c1ab57ea8805 src/arch/x86/tlb.hh c1ab57ea8805 src/arch/x86/tlb.cc c1ab57ea8805 src/arch/x86/utility.hh c1ab57ea8805 src/arch/x86/utility.cc c1ab57ea8805 src/arch/x86/vtophys.cc c1ab57ea8805 src/base/remote_gdb.cc c1ab57ea8805 src/base/vnc/SConscript c1ab57ea8805 src/cpu/BaseCPU.py c1ab57ea8805 src/cpu/SConscript c1ab57ea8805 src/cpu/base.hh c1ab57ea8805 src/cpu/base.cc c1ab57ea8805 src/cpu/base_dyn_inst.hh c1ab57ea8805 src/cpu/checker/cpu.hh c1ab57ea8805 src/cpu/checker/cpu.cc c1ab57ea8805 src/cpu/checker/cpu_impl.hh c1ab57ea8805 src/cpu/checker/thread_context.hh c1ab57ea8805 src/cpu/exec_context.hh c1ab57ea8805 src/cpu/exetrace.cc c1ab57ea8805 src/cpu/inorder/cpu.hh c1ab57ea8805 src/cpu/inorder/cpu.cc c1ab57ea8805 src/cpu/inorder/inorder_cpu_builder.cc c1ab57ea8805 src/cpu/inorder/inorder_dyn_inst.hh c1ab57ea8805 src/cpu/inorder/inorder_dyn_inst.cc c1ab57ea8805 src/cpu/inorder/params.hh c1ab57ea8805 src/cpu/inorder/resources/cache_unit.hh c1ab57ea8805 src/cpu/inorder/resources/cache_unit.cc c1ab57ea8805 src/cpu/inorder/resources/execution_unit.cc c1ab57ea8805 src/cpu/inorder/thread_context.hh c1ab57ea8805 src/cpu/inorder/thread_context.cc c1ab57ea8805 src/cpu/inorder/thread_state.hh c1ab57ea8805 src/cpu/inorder/thread_state.cc c1ab57ea8805 src/cpu/legiontrace.cc c1ab57ea8805 src/cpu/o3/O3CPU.py c1ab57ea8805 src/cpu/o3/checker_builder.cc c1ab57ea8805 src/cpu/o3/commit.hh c1ab57ea8805 src/cpu/o3/commit_impl.hh c1ab57ea8805 src/cpu/o3/cpu.hh c1ab57ea8805 src/cpu/o3/cpu.cc c1ab57ea8805 src/cpu/o3/cpu_builder.cc c1ab57ea8805 src/cpu/o3/decode_impl.hh c1ab57ea8805 src/cpu/o3/dyn_inst.hh c1ab57ea8805 src/cpu/o3/dyn_inst_impl.hh c1ab57ea8805 src/cpu/o3/fetch_impl.hh c1ab57ea8805 src/cpu/o3/iew.hh c1ab57ea8805 src/cpu/o3/lsq.hh c1ab57ea8805 src/cpu/o3/lsq_impl.hh c1ab57ea8805 src/cpu/o3/lsq_unit.hh c1ab57ea8805 src/cpu/o3/regfile.hh c1ab57ea8805 src/cpu/o3/rename_impl.hh c1ab57ea8805 src/cpu/o3/rob_impl.hh c1ab57ea8805 src/cpu/o3/thread_context.hh c1ab57ea8805 src/cpu/o3/thread_context_impl.hh c1ab57ea8805 src/cpu/o3/thread_state.hh c1ab57ea8805 src/cpu/ozone/SimpleOzoneCPU.py c1ab57ea8805 src/cpu/ozone/back_end_impl.hh c1ab57ea8805 src/cpu/ozone/checker_builder.cc c1ab57ea8805 src/cpu/ozone/cpu.hh c1ab57ea8805 src/cpu/ozone/cpu_builder.cc c1ab57ea8805 src/cpu/ozone/cpu_impl.hh c1ab57ea8805 src/cpu/ozone/dyn_inst.hh c1ab57ea8805 src/cpu/ozone/dyn_inst_impl.hh c1ab57ea8805 src/cpu/ozone/front_end_impl.hh c1ab57ea8805 src/cpu/ozone/inorder_back_end.hh c1ab57ea8805 src/cpu/ozone/inorder_back_end_impl.hh c1ab57ea8805 src/cpu/ozone/lsq_unit.hh c1ab57ea8805 src/cpu/ozone/lw_back_end_impl.hh c1ab57ea8805 src/cpu/ozone/lw_lsq.hh c1ab57ea8805 src/cpu/ozone/simple_cpu_builder.cc c1ab57ea8805 src/cpu/ozone/simple_params.hh c1ab57ea8805 src/cpu/ozone/thread_state.hh c1ab57ea8805 src/cpu/pc_event.cc c1ab57ea8805 src/cpu/simple/atomic.cc c1ab57ea8805 src/cpu/simple/base.hh c1ab57ea8805 src/cpu/simple/base.cc c1ab57ea8805 src/cpu/simple/timing.cc c1ab57ea8805 src/cpu/simple_thread.hh c1ab57ea8805 src/cpu/simple_thread.cc c1ab57ea8805 src/cpu/thread_context.hh c1ab57ea8805 src/cpu/thread_context.cc c1ab57ea8805 src/cpu/thread_state.hh c1ab57ea8805 src/cpu/thread_state.cc c1ab57ea8805 src/dev/Device.py c1ab57ea8805 src/dev/Pci.py c1ab57ea8805 src/dev/SConscript c1ab57ea8805 src/dev/Uart.py c1ab57ea8805 src/dev/alpha/AlphaBackdoor.py c1ab57ea8805 src/dev/alpha/SConscript c1ab57ea8805 src/dev/alpha/backdoor.cc c1ab57ea8805 src/dev/alpha/tsunami.hh c1ab57ea8805 src/dev/alpha/tsunami.cc c1ab57ea8805 src/dev/arm/RealView.py c1ab57ea8805 src/dev/arm/SConscript c1ab57ea8805 src/dev/arm/gic.hh c1ab57ea8805 src/dev/arm/gic.cc c1ab57ea8805 src/dev/arm/realview.hh c1ab57ea8805 src/dev/arm/realview.cc c1ab57ea8805 src/dev/baddev.cc c1ab57ea8805 src/dev/io_device.hh c1ab57ea8805 src/dev/io_device.cc c1ab57ea8805 src/dev/mips/SConscript c1ab57ea8805 src/dev/mips/malta.hh c1ab57ea8805 src/dev/mips/malta.cc c1ab57ea8805 src/dev/mips/malta_cchip.cc c1ab57ea8805 src/dev/mips/malta_io.cc c1ab57ea8805 src/dev/mips/malta_pchip.cc c1ab57ea8805 src/dev/pcidev.hh c1ab57ea8805 src/dev/pcidev.cc c1ab57ea8805 src/dev/platform.hh c1ab57ea8805 src/dev/sparc/SConscript c1ab57ea8805 src/dev/sparc/T1000.py c1ab57ea8805 src/dev/sparc/iob.cc c1ab57ea8805 src/dev/sparc/t1000.hh c1ab57ea8805 src/dev/sparc/t1000.cc c1ab57ea8805 src/dev/x86/SConscript c1ab57ea8805 src/dev/x86/i82094aa.hh c1ab57ea8805 src/dev/x86/i82094aa.cc c1ab57ea8805 src/dev/x86/pc.hh c1ab57ea8805 src/dev/x86/pc.cc c1ab57ea8805 src/kern/SConscript c1ab57ea8805 src/kern/kernel_stats.hh c1ab57ea8805 src/kern/kernel_stats.cc c1ab57ea8805 src/kern/linux/linux.hh c1ab57ea8805 src/kern/operatingsystem.hh c1ab57ea8805 src/kern/solaris/solaris.hh c1ab57ea8805 src/kern/tru64/tru64.hh c1ab57ea8805 src/mem/SConscript c1ab57ea8805 src/mem/cache/base.hh c1ab57ea8805 src/mem/cache/base.cc c1ab57ea8805 src/mem/page_table.cc c1ab57ea8805 src/mem/physical.cc c1ab57ea8805 src/mem/translating_port.hh c1ab57ea8805 src/mem/translating_port.cc c1ab57ea8805 src/mem/vport.hh c1ab57ea8805 src/python/swig/pyobject.cc c1ab57ea8805 src/sim/Root.py c1ab57ea8805 src/sim/SConscript c1ab57ea8805 src/sim/System.py c1ab57ea8805 src/sim/faults.hh c1ab57ea8805 src/sim/faults.cc c1ab57ea8805 src/sim/full_system.hh c1ab57ea8805 src/sim/process.hh c1ab57ea8805 src/sim/process.cc c1ab57ea8805 src/sim/process_impl.hh c1ab57ea8805 src/sim/pseudo_inst.hh c1ab57ea8805 src/sim/pseudo_inst.cc c1ab57ea8805 src/sim/root.cc c1ab57ea8805 src/sim/syscall_emul.hh c1ab57ea8805 src/sim/system.hh c1ab57ea8805 src/sim/system.cc c1ab57ea8805 src/sim/tlb.cc c1ab57ea8805 tests/SConscript c1ab57ea8805 tests/configs/inorder-timing.py c1ab57ea8805 tests/configs/memtest-ruby.py c1ab57ea8805 tests/configs/memtest.py c1ab57ea8805 tests/configs/o3-timing-mp-ruby.py c1ab57ea8805 tests/configs/o3-timing-mp.py c1ab57ea8805 tests/configs/o3-timing-ruby.py c1ab57ea8805 tests/configs/o3-timing.py c1ab57ea8805 tests/configs/pc-o3-timing.py c1ab57ea8805 tests/configs/pc-simple-atomic.py c1ab57ea8805 tests/configs/pc-simple-timing.py c1ab57ea8805 tests/configs/realview-o3-dual.py c1ab57ea8805 tests/configs/realview-o3.py c1ab57ea8805 tests/configs/realview-simple-atomic-dual.py c1ab57ea8805 tests/configs/realview-simple-atomic.py c1ab57ea8805 tests/configs/realview-simple-timing-dual.py c1ab57ea8805 tests/configs/realview-simple-timing.py c1ab57ea8805 tests/configs/rubytest-ruby.py c1ab57ea8805 tests/configs/simple-atomic-mp-ruby.py c1ab57ea8805 tests/configs/simple-atomic-mp.py c1ab57ea8805 tests/configs/simple-atomic.py c1ab57ea8805 tests/configs/simple-timing-mp-ruby.py c1ab57ea8805 tests/configs/simple-timing-mp.py c1ab57ea8805 tests/configs/simple-timing-ruby.py c1ab57ea8805 tests/configs/simple-timing.py c1ab57ea8805 tests/configs/t1000-simple-atomic.py c1ab57ea8805 tests/configs/tsunami-inorder.py c1ab57ea8805 tests/configs/tsunami-o3-dual.py c1ab57ea8805 tests/configs/tsunami-o3.py c1ab57ea8805 tests/configs/tsunami-simple-atomic-dual.py c1ab57ea8805 tests/configs/tsunami-simple-atomic.py c1ab57ea8805 tests/configs/tsunami-simple-timing-dual.py c1ab57ea8805 tests/configs/tsunami-simple-timing.py c1ab57ea8805 tests/configs/twosys-tsunami-simple-atomic.py c1ab57ea8805 tests/run.py c1ab57ea8805 Diff: http://reviews.m5sim.org/r/928/diff Testing ------- Ran quick regressions for all ISAs and one RUBY specific ALPHA configuration. Thanks, Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
