Oooooooh. These are apparently a problem when you compile gem5.fast. I
bet I didn't even think to try that. I fixed the problems with gem5.opt,
and I think there were a lot more than what's here. Phew, I'm not crazy!

Gabe

On 12/13/11 14:51, Nathan Binkert wrote:
> changeset f9e22de34149 in /z/repo/gem5
> details: http://repo.gem5.org/gem5?cmd=changeset;node=f9e22de34149
> description:
>       gcc: fix unused variable warnings from GCC 4.6.1
>
> diffstat:
>
>  src/arch/arm/nativetrace.cc           |  12 +++++++++---
>  src/base/remote_gdb.cc                |   3 +--
>  src/cpu/o3/fetch_impl.hh              |   4 ++--
>  src/dev/i8254xGBe.cc                  |   7 ++++---
>  src/dev/ide_ctrl.cc                   |   2 ++
>  src/dev/sinic.cc                      |   5 ++++-
>  src/dev/sparc/mm_disk.cc              |  32 ++++++++++++++++++++++----------
>  src/dev/terminal.cc                   |   8 ++------
>  src/mem/page_table.cc                 |   8 ++------
>  src/mem/ruby/system/SConscript        |   2 +-
>  src/mem/ruby/system/Sequencer.cc      |  10 ++++------
>  src/mem/slicc/ast/PeekStatementAST.py |   2 +-
>  src/mem/slicc/symbols/StateMachine.py |   1 +
>  13 files changed, 55 insertions(+), 41 deletions(-)
>
> diffs (truncated from 321 to 300 lines):
>
> diff -r c1ab57ea8805 -r f9e22de34149 src/arch/arm/nativetrace.cc
> --- a/src/arch/arm/nativetrace.cc     Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/arch/arm/nativetrace.cc     Tue Dec 13 11:49:27 2011 -0800
> @@ -156,18 +156,23 @@
>      // Regular int regs
>      for (int i = 0; i < STATE_NUMVALS; i++) {
>          if (nState.changed[i] || mState.changed[i]) {
> -            const char *vergence = "  ";
>              bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
>              bool newMatch = (mState.newState[i] == nState.newState[i]);
>              if (oldMatch && newMatch) {
>                  // The more things change, the more they stay the same.
>                  continue;
> -            } else if (oldMatch && !newMatch) {
> +            }
> +
> +            errorFound = true;
> +
> +#ifndef NDEBUG
> +            const char *vergence = "  ";
> +            if (oldMatch && !newMatch) {
>                  vergence = "<>";
>              } else if (!oldMatch && newMatch) {
>                  vergence = "><";
>              }
> -            errorFound = true;
> +
>              if (!nState.changed[i]) {
>                  DPRINTF(ExecRegDelta, "%s [%5s] "\
>                                        "Native:         %#010x         "\
> @@ -190,6 +195,7 @@
>                                        nState.oldState[i], nState.newState[i],
>                                        mState.oldState[i], 
> mState.newState[i]);
>              }
> +#endif
>          }
>      }
>      if (errorFound) {
> diff -r c1ab57ea8805 -r f9e22de34149 src/base/remote_gdb.cc
> --- a/src/base/remote_gdb.cc  Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/base/remote_gdb.cc  Tue Dec 13 11:49:27 2011 -0800
> @@ -648,8 +648,7 @@
>      bufferSize = gdbregs.bytes() * 2 + 256;
>      buffer = (char*)malloc(bufferSize);
>  
> -    TheISA::PCState pc = context->pcState();
> -    DPRINTF(GDBMisc, "trap: PC=%s\n", pc);
> +    DPRINTF(GDBMisc, "trap: PC=%s\n", context->pcState());
>  
>      clearSingleStep();
>  
> diff -r c1ab57ea8805 -r f9e22de34149 src/cpu/o3/fetch_impl.hh
> --- a/src/cpu/o3/fetch_impl.hh        Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/cpu/o3/fetch_impl.hh        Tue Dec 13 11:49:27 2011 -0800
> @@ -1053,8 +1053,8 @@
>  
>          if (fetchStatus[tid] != Squashing) {
>  
> -            TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
> -            DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
> +            DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
> +                fromDecode->decodeInfo[tid].nextPC);
>              // Squash unless we're already squashing
>              squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
>                               fromDecode->decodeInfo[tid].squashInst,
> diff -r c1ab57ea8805 -r f9e22de34149 src/dev/i8254xGBe.cc
> --- a/src/dev/i8254xGBe.cc    Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/dev/i8254xGBe.cc    Tue Dec 13 11:49:27 2011 -0800
> @@ -2118,11 +2118,12 @@
>      // iteration we'll get the rest of the data
>      if (txPacket && txDescCache.packetAvailable()
>          && !txDescCache.packetMultiDesc() && txPacket->length) {
> -        bool success;
> -
>          anQ("TXS", "TX FIFO Q");
>          DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
> -        success = txFifo.push(txPacket);
> +#ifndef NDEBUG
> +        bool success =
> +#endif
> +            txFifo.push(txPacket);
>          txFifoTick = true && !drainEvent;
>          assert(success);
>          txPacket = NULL;
> diff -r c1ab57ea8805 -r f9e22de34149 src/dev/ide_ctrl.cc
> --- a/src/dev/ide_ctrl.cc     Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/dev/ide_ctrl.cc     Tue Dec 13 11:49:27 2011 -0800
> @@ -490,6 +490,7 @@
>          panic("IDE controller access to invalid address: %#x\n", addr);
>      }
>  
> +#ifndef NDEBUG
>      uint32_t data;
>      if (pkt->getSize() == 1)
>          data = pkt->get<uint8_t>();
> @@ -499,6 +500,7 @@
>          data = pkt->get<uint32_t>();
>      DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
>              read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
> +#endif
>  
>      pkt->makeAtomicResponse();
>  }
> diff -r c1ab57ea8805 -r f9e22de34149 src/dev/sinic.cc
> --- a/src/dev/sinic.cc        Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/dev/sinic.cc        Tue Dec 13 11:49:27 2011 -0800
> @@ -33,6 +33,7 @@
>  #include <string>
>  
>  #include "arch/vtophys.hh"
> +#include "base/compiler.hh"
>  #include "base/debug.hh"
>  #include "base/inet.hh"
>  #include "base/types.hh"
> @@ -404,7 +405,7 @@
>  
>      prepareRead(cpu, index);
>  
> -    uint64_t value = 0;
> +    uint64_t value M5_VAR_USED = 0;
>      if (pkt->getSize() == 4) {
>          uint32_t reg = regData32(raddr);
>          pkt->set(reg);
> @@ -916,6 +917,7 @@
>                  VirtualReg *vn = &virtualRegs[i];
>                  bool busy = Regs::get_RxDone_Busy(vn->RxDone);
>                  if (vn->rxIndex != end) {
> +#ifndef NDEBUG
>                      bool dirty = vn->rxPacketOffset > 0;
>                      const char *status;
>  
> @@ -933,6 +935,7 @@
>                              i, status, vn->rxUnique,
>                              rxFifo.countPacketsBefore(vn->rxIndex),
>                              vn->rxIndex->slack);
> +#endif
>                  } else if (busy) {
>                      DPRINTF(EthernetSM, "vnic %d unmapped (rxunique %d)\n",
>                              i, vn->rxUnique);
> diff -r c1ab57ea8805 -r f9e22de34149 src/dev/sparc/mm_disk.cc
> --- a/src/dev/sparc/mm_disk.cc        Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/dev/sparc/mm_disk.cc        Tue Dec 13 11:49:27 2011 -0800
> @@ -56,7 +56,6 @@
>  {
>      Addr accessAddr;
>      off_t sector;
> -    off_t bytes_read;
>      uint16_t d16;
>      uint32_t d32;
>      uint64_t d64;
> @@ -68,10 +67,16 @@
>  
>      if (sector != curSector) {
>          if (dirty) {
> -            bytes_read = image->write(diskData, curSector);
> -            assert(bytes_read == SectorSize);
> +#ifndef NDEBUG
> +            off_t bytes_written =
> +#endif
> +                image->write(diskData, curSector);
> +            assert(bytes_written == SectorSize);
>          }
> -        bytes_read = image->read(diskData,  sector);
> +#ifndef NDEBUG
> +        off_t bytes_read =
> +#endif
> +            image->read(diskData, sector);
>          assert(bytes_read == SectorSize);
>          curSector = sector;
>      }
> @@ -109,7 +114,6 @@
>  {
>      Addr accessAddr;
>      off_t sector;
> -    off_t bytes_read;
>      uint16_t d16;
>      uint32_t d32;
>      uint64_t d64;
> @@ -121,10 +125,16 @@
>  
>      if (sector != curSector) {
>          if (dirty) {
> -            bytes_read = image->write(diskData, curSector);
> -            assert(bytes_read == SectorSize);
> +#ifndef NDEBUG
> +            off_t bytes_written =
> +#endif
> +                image->write(diskData, curSector);
> +            assert(bytes_written == SectorSize);
>          }
> -        bytes_read = image->read(diskData,  sector);
> +#ifndef NDEBUG
> +        off_t bytes_read =
> +#endif
> +            image->read(diskData,  sector);
>          assert(bytes_read == SectorSize);
>          curSector = sector;
>      }
> @@ -164,9 +174,11 @@
>  {
>      // just write any dirty changes to the cow layer it will take care of
>      // serialization
> -    int bytes_read;
>      if (dirty) {
> -        bytes_read = image->write(diskData, curSector);
> +#ifndef NDEBUG
> +        int bytes_read =
> +#endif
> +            image->write(diskData, curSector);
>          assert(bytes_read == SectorSize);
>      }
>  }
> diff -r c1ab57ea8805 -r f9e22de34149 src/dev/terminal.cc
> --- a/src/dev/terminal.cc     Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/dev/terminal.cc     Tue Dec 13 11:49:27 2011 -0800
> @@ -259,17 +259,13 @@
>  uint8_t
>  Terminal::in()
>  {
> -    bool empty;
>      uint8_t c;
>  
> -    empty = rxbuf.empty();
> -    assert(!empty);
> +    assert(!rxbuf.empty());
>      rxbuf.read((char *)&c, 1);
> -    empty = rxbuf.empty();
> -
>  
>      DPRINTF(TerminalVerbose, "in: \'%c\' %#02x more: %d\n",
> -            isprint(c) ? c : ' ', c, !empty);
> +            isprint(c) ? c : ' ', c, !rxbuf.empty());
>  
>      return c;
>  }
> diff -r c1ab57ea8805 -r f9e22de34149 src/mem/page_table.cc
> --- a/src/mem/page_table.cc   Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/mem/page_table.cc   Tue Dec 13 11:49:27 2011 -0800
> @@ -93,9 +93,7 @@
>              new_vaddr, size);
>  
>      for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += 
> pageSize) {
> -        PTableItr iter = pTable.find(vaddr);
> -
> -        assert(iter != pTable.end());
> +        assert(pTable.find(vaddr) != pTable.end());
>  
>          pTable[new_vaddr] = pTable[vaddr];
>          pTable.erase(vaddr);
> @@ -112,9 +110,7 @@
>      DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
>  
>      for (; size > 0; size -= pageSize, vaddr += pageSize) {
> -        PTableItr iter = pTable.find(vaddr);
> -
> -        assert(iter != pTable.end());
> +        assert(pTable.find(vaddr) != pTable.end());
>  
>          pTable.erase(vaddr);
>      }
> diff -r c1ab57ea8805 -r f9e22de34149 src/mem/ruby/system/SConscript
> --- a/src/mem/ruby/system/SConscript  Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/mem/ruby/system/SConscript  Tue Dec 13 11:49:27 2011 -0800
> @@ -49,6 +49,6 @@
>  Source('MemoryNode.cc')
>  Source('PersistentTable.cc')
>  Source('RubyPort.cc')
> -Source('Sequencer.cc', Werror=False)
> +Source('Sequencer.cc')
>  Source('System.cc')
>  Source('TimerTable.cc')
> diff -r c1ab57ea8805 -r f9e22de34149 src/mem/ruby/system/Sequencer.cc
> --- a/src/mem/ruby/system/Sequencer.cc        Thu Dec 01 17:36:22 2011 -0800
> +++ b/src/mem/ruby/system/Sequencer.cc        Tue Dec 13 11:49:27 2011 -0800
> @@ -221,10 +221,8 @@
>  RequestStatus
>  Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
>  {
> -    int total_outstanding =
> -        m_writeRequestTable.size() + m_readRequestTable.size();
> -
> -    assert(m_outstanding_count == total_outstanding);
> +    assert(m_outstanding_count ==
> +        (m_writeRequestTable.size() + m_readRequestTable.size()));
>  
>      // See if we should schedule a deadlock check
>      if (deadlockCheckEvent.scheduled() == false) {
> @@ -285,8 +283,8 @@
>      }
>  
>      g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
> -    total_outstanding = m_writeRequestTable.size() + 
> m_readRequestTable.size();
> -    assert(m_outstanding_count == total_outstanding);
> +    assert(m_outstanding_count ==
> +        (m_writeRequestTable.size() + m_readRequestTable.size()));
>  
>      return RequestStatus_Ready;
>  }
> diff -r c1ab57ea8805 -r f9e22de34149 src/mem/slicc/ast/PeekStatementAST.py
> --- a/src/mem/slicc/ast/PeekStatementAST.py   Thu Dec 01 17:36:22 2011 -0800
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