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Review request for Default. Summary ------- MEM: Add the system port as a central access point The system port is used as a globally reachable access point to the memory subsystem. The benefit of using an actual port is that the usual infrastructure is used to resolve any access and thus makes the overall system able to handle distributed memories in any configuration, and also makes the accesses agnostic to the address map. This patch only introduces the port and does not actually use it for anything. Diffs ----- src/python/m5/SimObject.py ca98021c3f96 src/python/m5/simulate.py ca98021c3f96 src/sim/System.py ca98021c3f96 src/sim/sim_object.hh ca98021c3f96 src/sim/sim_object.cc ca98021c3f96 src/sim/system.hh ca98021c3f96 src/sim/system.cc ca98021c3f96 Diff: http://reviews.m5sim.org/r/942/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
