> On 2012-01-01 16:53:39, Ali Saidi wrote: > > src/cpu/o3/commit_impl.hh, line 721 > > <http://reviews.m5sim.org/r/961/diff/1/?file=16810#file16810line721> > > > > How can an instruction not be in the instList, but be partly inflight?
Please read this email -- http://www.mail-archive.com/[email protected]/msg01945.html and if possible, the entire thread. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/961/#review1793 ----------------------------------------------------------- On 2011-12-30 16:38:31, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/961/ > ----------------------------------------------------------- > > (Updated 2011-12-30 16:38:31) > > > Review request for Default. > > > Summary > ------- > > O3 CPU: Add a boolean flag for instruction midway in execution > This patch adds a boolean flag to the commit stage of the O3 cpu for > tracking whether or not there is an instruction that has committed some but > not all of its microops. This is required so that the interrupts are not > handled while an instruction is midway through its execution. > > > Diffs > ----- > > src/cpu/o3/commit.hh ca98021c3f96 > src/cpu/o3/commit_impl.hh ca98021c3f96 > src/cpu/o3/iew.hh ca98021c3f96 > > Diff: http://reviews.m5sim.org/r/961/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
