----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/951/#review1816 -----------------------------------------------------------
- Ali On 2011-12-23 01:35:57, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/951/ > ----------------------------------------------------------- > > (Updated 2011-12-23 01:35:57) > > > Review request for Default. > > > Summary > ------- > > MEM: Make the bus bridge unidirectional and fixed address range > > This patch makes the bus bridge uni-directional and specialises the > bus ports to be a master port and a slave port. This greatly > simplifies the assumptions on both sides as either port only has to > deal with requests or responses. The following patches introduce the > notion of master and slave ports, and would not be possible without > this split of responsibilities. > > In making the bridge unidirectional, the address range mechanism of > the bridge is also changed. For the cases where communication is > taking place both ways, an additional bridge is needed. This causes > issues with the existing mechanism, as the busses cannot determine > when to stop iterating the address updates from the two bridges. To > avoid this issue, and also greatly simplify the specification, the > bridge now has a fixed set of address ranges, specified at creation > time. > > > Diffs > ----- > > configs/common/FSConfig.py ca98021c3f96 > src/dev/arm/RealView.py ca98021c3f96 > src/mem/Bridge.py ca98021c3f96 > src/mem/bridge.hh ca98021c3f96 > src/mem/bridge.cc ca98021c3f96 > tests/configs/pc-o3-timing.py ca98021c3f96 > tests/configs/pc-simple-atomic.py ca98021c3f96 > tests/configs/pc-simple-timing.py ca98021c3f96 > tests/configs/realview-o3-dual.py ca98021c3f96 > tests/configs/realview-o3.py ca98021c3f96 > tests/configs/realview-simple-atomic-dual.py ca98021c3f96 > tests/configs/realview-simple-atomic.py ca98021c3f96 > tests/configs/realview-simple-timing-dual.py ca98021c3f96 > tests/configs/realview-simple-timing.py ca98021c3f96 > tests/configs/tsunami-inorder.py ca98021c3f96 > tests/configs/tsunami-o3-dual.py ca98021c3f96 > tests/configs/tsunami-o3.py ca98021c3f96 > tests/configs/tsunami-simple-atomic-dual.py ca98021c3f96 > tests/configs/tsunami-simple-atomic.py ca98021c3f96 > tests/configs/tsunami-simple-timing-dual.py ca98021c3f96 > tests/configs/tsunami-simple-timing.py ca98021c3f96 > tests/configs/twosys-tsunami-simple-atomic.py ca98021c3f96 > > Diff: http://reviews.m5sim.org/r/951/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
